Fully Capacitive Coupled Input Choppers
A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.
1. Field of the Invention
The present invention relates to the field of input choppers for such uses as in operational amplifiers, instrumentation amplifiers and analog-to-digital converters.
2. Prior Art
Instrumentation amplifiers and analog-to-digital converters are frequently used for sensor interfacing. In current-sense applications for power management of cell phones, laptops, and electric cars, a small differential-mode voltage in the order of millivolts has to be measured across a current-sense resistor in the presence of a large common-mode voltage on the sense resistor on the order of Volts or tens of Volts higher than the supply voltage. To solve this differential-mode voltage measurement problem while the common-mode voltage is beyond the supply-rail, often a part of the input circuitry (which may be a resistor bridge or a voltage-to-current converter) is allowed to draw its common-mode supply current from the sense resistor. This input common-mode supply current often has an undesired influence on the system to be measured. Therefore, instrumentation amplifiers and analog-to-digital converters with capacitive-coupled input choppers have been developed that do not draw input common-mode supply current, while being able to sense beyond their supply-rail voltage. One such prior art technique is to use an input chopper followed by a capacitive coupled differential input. A second chopper rectifies the square wave back into the input waveform.
Another prior art technique is to use transformers, as shown in U.S. Pat. No. 7,714,757. That solution is expensive to implement, both in cost and in circuit board area, as it cannot easily be fully integrated.
A disadvantage of the capacitive coupled chopper with the diode-protected gates of
Now referring to
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Transistors MN5-MN8 are each also in respective floating n-wells. In that regard, the other embodiments disclosed herein all use floating wells in a similar manner, though the back-to-back diodes are not shown in the other Figs. to avoid unnecessary clutter and not obscure the details of the circuits disclosed.
Considering first transistors MN1 and MN5, when Clkn goes high and Clkp is low, transistor MN5 will turn on to the extent required to bring its drain equal to its source voltage, namely, the input voltage Vinp. With the drain of transistor MN5 at the voltage Vinp, transistor MN1 will still be off, as its gate voltage will be equal to its source voltage, while chopper transistor MN3 turns on. Then when Clkn goes low, transistor MN5 is turned off and of course Clkp goes high, turning on transistor MN1, and turning transistor MN3 off. Thus transistor MN5 determines or sets the voltage on the gates of transistor MN1 and MN7 when Clkn is high based in the input Vinp, which gate connections are otherwise effectively floating. Transistor MN7 functions similarly for transistor M3, as does transistor MN6 for transistor MN2 and transistor MN8 for transistor MN4.
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An improvement of the circuit of
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The capacitive coupled input choppers can be used in operational amplifiers, instrumentation amplifiers, and analog-to-digital converters, as exemplified in
Thus the floating input choppers consist of four transistors MN1-4. These transistors are placed in isolated pockets. Their gates are coupled to the clock signals by series capacitors. In the embodiment of
Thus the present invention has a number of aspects, which aspects may be practiced alone or in various combinations or sub-combinations, as desired. While a preferred embodiment of the present invention has been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the full breadth of the following claims.
Claims
1. A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage, comprising:
- providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input;
- providing an output chopper;
- capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper;
- capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being capacitively coupled to the gates of the first and second transistors and the second phase being capacitively coupled to the gates of the third and fourth transistors; and,
- providing protection of the gates of the first through fourth transistors from excessive voltages.
2. The method of claim 1 wherein the first through fourth transistors are MOS transistors, and wherein the sources of the first and third transistors are coupled to the Vinp input, the sources of the second and fourth transistors are coupled to the Vinn input, the drains of the first and fourth transistors are coupled to input chopper output Voutp and the drains of the second and third transistors being coupled to the input chopper output Voutn.
3. The method of claim 2 wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises coupling diodes between the respective gates and sources of the first through fourth transistors, some in a series connection with a polarity to limit the gate source voltage tending to turn on the respective transistor and at least one diode of the opposite polarity between the respective sources and drains.
4. The method of claim 2 further comprised of providing protection of the first through fourth transistors from excessive drain source voltages.
5. The method of claim 4 wherein providing protection of the first through fourth transistors from excessive drain source voltages comprises coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diode.
6. The method of claim 2 further comprised of providing protection for the first through fourth transistors against a negative common mode input voltage step.
7. The method of claim 6 wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises, when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, coupling the gates of the first and third transistors to the input Vinp, and coupling the gates of the second and fourth transistors to the input Vinn.
8. The method of claim 7 wherein the coupling the gates of the first and third transistors to the input Vinp comprises capacitively coupling a diode connected fifth transistor between ground and the input Vinp, and coupling first replica transistors to the gates of the first and third transistors, the first replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the first replica transistors when a negative surge on the input Vinp reverses the voltage across the diode connected fifth transistor, and wherein the coupling the gates of the second and fourth transistors to the input Vinn comprises capacitively coupling a diode connected sixth transistor between ground and the input Vinn, and coupling second replica transistors to the gates of the second and fourth transistors, the second replica transistors replicating a conduction state of the diode connected sixth transistor to turn on when a negative surge on the input Vinn reverses the voltage across the diode connected sixth transistor.
9. The method of claim 8 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.
10. The method of claim 6 wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises, when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, coupling the gates of the first through fourth transistors to the input Vinp or the input Vinn, which ever is a lower voltage.
11. The method of claim 10 wherein the coupling the gates of the first through fourth transistors to the input Vinp or the input Vinn, which ever is a lower voltage comprises capacitively coupling a diode connected fifth transistor between ground and the input Vinp or Vinn, which ever has a lower voltage, and coupling a first one replica transistor to the gates of the first and second transistors and coupling a second replica transistor to the gates of the third and fourth transistors, the replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the replica transistors when a negative surge on the input Vinp or Vinn, which ever is a lower voltage, reverses the voltage across the diode connected fifth transistor.
12. The method of claim 11 wherein which of the inputs Vinp or Vinn is a lower voltage is determined by providing a latch responsive the inputs Vinp and Vinn.
13. The method of claim 12 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.
14. The method of claim 6 wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises, when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, coupling the gates of the first through fourth transistors to one of the inputs Vinp or Vinn.
15. The method of claim 14 wherein coupling the gates of the first and second transistors to the input Vinp or Vinn comprises capacitively coupling a diode connected fifth transistor between ground and the respective input Vinp or Vinn, and coupling a first replica transistor to the gates of the first and second transistors and coupling a second replica transistor to the gates of the third and fourth transistors, the replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the replica transistors when a negative surge on the input coupled to the diode connected fifth transistor reverses the voltage across the diode connected fifth transistor.
16. The method of claim 15 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.
17. The method of claim 15 further comprising:
- accurately defining the start voltages of the gates of the first through fourth transistors for a next clock inversion by providing a latch having a first latch connection to the gates of the first and second transistors, and a second latch connection to the gates of the third and fourth transistors, respectively.
18. The method of claim 2 further comprising:
- accurately defining the start voltages of the gates of transistors MN1 through MN4 for a next clock inversion by providing a first latch having a first latch connection coupled to the gates of the first and second transistors, and a second latch connection coupled to the gates of the third and fourth transistors, respectively, the latch having a common connection coupled to one to one of the inputs Vinp and Vinn.
19. The method of claim 18 further comprising:
- accurately defining the start voltages of the gates of the first through eighth transistors for a next clock inversion by providing a first latch between the gates of the first and second transistors, a second latch between the gates of the third and fourth transistors, a third latch between the fifth and sixth transistors and a fourth latch between the seventh and eighth transistors, respectively, the first latch having a common connection coupled to the input Vinp, the second latch having a common connection coupled to the input Vinn, the third latch having a common connection coupled to the input chopper output Voutn, and the fourth latch having a common connection coupled to the input chopper output Voutp.
Type: Application
Filed: Dec 14, 2011
Publication Date: Jun 20, 2013
Patent Grant number: 9143092
Applicant: MAXIM INTEGRATED PRODUCTS, INC. (Sunnyvale, CA)
Inventors: Johan Hendrik Huijsing (Schipluiden), Qinwen Fan (Delft), Kofi Afolabi Anthony Makinwa (Delft)
Application Number: 13/325,847
International Classification: H03K 17/687 (20060101);