Abstract: An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: A switch mode power supply (SMPS) and method are provided. In particular, the present invention provides an SMPS in which data is encoded by manipulating voltage pulses on a primary side. The manipulated voltage pulses are then transferred over a transformer to a secondary side. Secondary side pulses generated in response to the primary side pulses are sensed and decoded by a detector. The present invention allows data to be transferred from the primary side to the secondary side without affecting output voltages.

Abstract: A switch mode power supply (SMPS) and method are provided. In particular, the present invention provides an SMPS in which data is encoded by manipulating voltage pulses on a primary side. The manipulated voltage pulses are then transferred over a transformer to a secondary side. Secondary side pulses generated in response to the primary side pulses are sensed and decoded by a detector. The present invention allows data to be transferred from the primary side to the secondary side without affecting output voltages.

Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: A method for reducing harmonic distortions and switching losses in a power factor correction circuit of a quasi-resonant voltage converter, wherein using data derived from the sensing a voltage impressed on the switching device in the power converter, a multitude of event times can be calculated that will align the timings of the drive circuitry of the power converter to those of the natural resonance transitions of reactive elements of the converter. An over-sampling of the voltage impressed on the switching device voltage allows accurate sensing of a “zero-current” cross-over condition in an inductance of the converter.

Abstract: A power supply comprising a flyback converter and a controller is disclosed. The flyback converter drives a load when electrically coupled to an alternating current power source. The controller controls a soft switching during each switching time period of the flyback converter. Upon an initial switching time period, the controller determines each acceptable switching frequency for the subsequent switching time periods and selects one of the acceptable switching frequencies for soft switching the flyback converter over one or more switching time periods during a constant load.

Abstract: A ballast system in which mixed-mode gate signals are used to control the ballast circuit so as to produce a more straight ballast lines such than only a single solution exists between ballast lines and lamp lines over the whole operating range, whereby a stable of lamp performance is achieved. In a preferred embodiment, symmetric and asymmetric modes are arranged alternatively in every other switching cycle to produce mixed-mode PWM gate signals.

Abstract: A method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from the FSG dielectric layer, comprising the following steps. A semiconductor structure having a metal structure, with an overlying liner layer, formed thereover is provided. A FSG dielectric layer is formed over the liner layer. The FSG dielectric layer having an exposed upper surface. The FSG dielectric layer is treated with a first nitrogen gas/plasma treatment to form a fluorine depleted upper capping layer from the exposed surface of the FSG dielectric layer. A TEOS oxide layer is formed over the upper capping layer. The TEOS oxide layer is planarized to form a planarized TEOS oxide layer. The planarized TEOS oxide layer, the upper capping layer, the treated FSG dielectric layer, and the liner layer are patterned to form a via hole therethrough, exposing a portion of the metal structure and exposing sidewalls of the patterned treated FSG dielectric layer within the via opening.