Patents by Inventor Qiong Yu
Qiong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9601531Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads and the scribe line regions; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. The second dike structures are arranged corresponding to the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures and the first dike structures.Type: GrantFiled: August 1, 2014Date of Patent: March 21, 2017Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
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Patent number: 9455298Abstract: A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via laser in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor.Type: GrantFiled: February 1, 2016Date of Patent: September 27, 2016Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhi-Qi Wang, Qiong Yu, Wei Wang
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Publication number: 20160148972Abstract: A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via laser in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor.Type: ApplicationFiled: February 1, 2016Publication date: May 26, 2016Inventors: Zhi-Qi WANG, Qiong YU, Wei WANG
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Patent number: 9305961Abstract: A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via a first blade in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a second blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor.Type: GrantFiled: January 8, 2014Date of Patent: April 5, 2016Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhi-Qi Wang, Qiong Yu, Wei Wang
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Patent number: 9299735Abstract: Image sensor package structure and method are provided. The method includes: providing first substrate having upper surface on which image sensing areas and pads are formed; providing second substrate having through holes; forming tape film on upper surface of second substrate to seal each through hole; contacting lower surface of second substrate with upper surface of first substrate to make image sensing areas in through holes; removing portions of tape film and second substrate, wherein remained tape film and second substrate form cavities including sidewalls made of second substrate and caps sealing sidewalls and made of tape film, and remained second substrate also covers pads; removing portions of remained second substrate to expose pads; slicing first substrate to form single image sensor chips including image sensing areas and pads; and electrically connecting pads with circuits on third substrate through wires. Pollution or damage to image sensing areas may be avoided.Type: GrantFiled: August 19, 2014Date of Patent: March 29, 2016Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
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Wafer level packaging structure for image sensors and wafer level packaging method for image sensors
Patent number: 9231018Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. Projections of the second dike structures onto the first surface of the wafer are included in the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures, while tops of the first dike structures and the surface of the packaging cover are contacted.Type: GrantFiled: August 1, 2014Date of Patent: January 5, 2016Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Qiong Yu, Wei Wang -
Publication number: 20150200153Abstract: A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second chip comprises a third surface and a fourth surface, a second plurality of pads are disposed on the third surface; combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of the combination area of the first chip and the second chip; and forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip. Processes of the method are simple, and the chip package is small.Type: ApplicationFiled: January 6, 2015Publication date: July 16, 2015Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Junjie Li, Ying Yang, Qiong Yu, Wei Wang
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Publication number: 20150137294Abstract: Image sensor package structure and method are provided. The method includes: providing first substrate having upper surface on which image sensing areas and pads are formed; providing second substrate having through holes; forming tape film on upper surface of second substrate to seal each through hole; contacting lower surface of second substrate with upper surface of first substrate to make image sensing areas in through holes; removing portions of tape film and second substrate, wherein remained tape film and second substrate form cavities including sidewalls made of second substrate and caps sealing sidewalls and made of tape film, and remained second substrate also covers pads; removing portions of remained second substrate to expose pads; slicing first substrate to form single image sensor chips including image sensing areas and pads; and electrically connecting pads with circuits on third substrate through wires. Pollution or damage to image sensing areas may be avoided.Type: ApplicationFiled: August 19, 2014Publication date: May 21, 2015Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
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WAFER LEVEL PACKAGING STRUCTURE FOR IMAGE SENSORS AND WAFER LEVEL PACKAGING METHOD FOR IMAGE SENSORS
Publication number: 20150054108Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. Projections of the second dike structures onto the first surface of the wafer are included in the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures, while tops of the first dike structures and the surface of the packaging cover are contacted.Type: ApplicationFiled: August 1, 2014Publication date: February 26, 2015Inventors: Zhiqi Wang, Qiong Yu, Wei Wang -
WAFER LEVEL PACKAGING STRUCTURE FOR IMAGE SENSORS AND WAFER LEVEL PACKAGING METHOD FOR IMAGE SENSORS
Publication number: 20150054109Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads and the scribe line regions; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. The second dike structures are arranged corresponding to the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures and the first dike structures.Type: ApplicationFiled: August 1, 2014Publication date: February 26, 2015Inventors: Zhiqi Wang, Qiong Yu, Wei Wang -
Patent number: 8814044Abstract: An intellectual material object management method includes: an RF scanning device scans a carrier tag of a replenishment carrier and a shelf tag of at least one present supplying shelf among stock shelves of a warehouse to assist for putting the replenishment carrier on a target shelf for the replenishment carrier. An MO picking list for obtaining information of at least one selected MO is received. The RF scanning device scans an MO tag of a present picking MO on a present picking shelf among the stock shelves and a list tag of the MO picking list to assist for obtaining the selected MO from the stock shelves of the warehouse. A remaining amount of remaining MOs is counted. An amount tag for the remaining MOs is printed according to the remaining amount of the remaining MOs for sticking on a remaining MO carrier for loading the remaining MOs.Type: GrantFiled: August 1, 2012Date of Patent: August 26, 2014Assignee: Wistron Corp.Inventors: Li Yuan, Tai-Hsin Chou, Qiong-Yu Niu, Tian-Heng Zhao
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Publication number: 20140191352Abstract: A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via a first blade in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a second blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor.Type: ApplicationFiled: January 8, 2014Publication date: July 10, 2014Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhi-Qi WANG, Qiong YU, Wei WANG
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Patent number: 8748669Abstract: Provided is a process for producing aldehydes or ketones by oxidizing alcohols with oxygen, which comprises oxidizing alcohols to aldehydes or ketones in an organic solvent at room temperature with oxygen or air as an oxidant, wherein ferric nitrate (Fe(NO3)3.9H2O), 2,2,6,6-tetramethylpiperidine N-oxyl (TEMPO) and an inorganic chloride are used as catalysts, the reaction time is 1-24 hours, and the molar ratio of said alcohols, 2,2,6,6-tetramethylpiperidine N-oxyl and the inorganic chloride is 100:1˜10:1˜10:1˜10. The present process has the advantages of high yield, mild reaction conditions, simple operation, convenient separation and purification, recoverable solvents, substrates used therefor being various and no pollution, and therefore it is adaptable to industrialization.Type: GrantFiled: July 30, 2010Date of Patent: June 10, 2014Assignees: East China Normal University, Shanghai Institute of Organic Chemistry, Chinese Academy of SciencesInventors: Shengming Ma, Jinxian Liu, Jinqiang Kuang, Yu Liu, Yuli Wang, Qiong Yu, Weiming Yuan, Suhua Li, Bo Chen, Jiajia Cheng, Baoqiang Wan, Juntao Ye, Shichao Yu
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Publication number: 20130248597Abstract: An intellectual material object management method includes: an RF scanning device scans a carrier tag of a replenishment carrier and a shelf tag of at least one present supplying shelf among stock shelves of a warehouse to assist for putting the replenishment carrier on a target shelf for the replenishment carrier. An MO picking list for obtaining information of at least one selected MO is received. The RF scanning device scans an MO tag of a present picking MO on a present picking shelf among the stock shelves and a list tag of the MO picking list to assist for obtaining the selected MO from the stock shelves of the warehouse. A remaining amount of remaining MOs is counted. An amount tag for the remaining MOs is printed according to the remaining amount of the remaining MOs for sticking on a remaining MO carrier for loading the remaining MOs.Type: ApplicationFiled: August 1, 2012Publication date: September 26, 2013Applicant: WISTRON CORP.Inventors: Li YUAN, Tai-Hsin CHOU, Qiong-Yu NIU, Tian-Heng ZHAO
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Publication number: 20120220792Abstract: Provided is a process for producing aldehydes or ketones by oxidizing alcohols with oxygen, which comprises oxidizing alcohols to aldehydes or ketones in an organic solvent at room temperature with oxygen or air as an oxidant, wherein ferric nitrate (Fe(NO3)3.9H2O), 2,2,6,6-tetramethylpiperidine N-oxyl (TEMPO) and an inorganic chloride are used as catalysts, the reaction time is 1-24 hours, and the molar ratio of said alcohols, 2,2,6,6-tetramethylpiperidine N-oxyl and the inorganic chloride is 100:1˜10:1˜10:1˜10. The present process has the advantages of high yield, mild reaction conditions, simple operation, convenient separation and purification, recoverable solvents, substrates used therefor being various and no pollution, and therefore it is adaptable to industrialization.Type: ApplicationFiled: July 30, 2010Publication date: August 30, 2012Inventors: Shengming Ma, Jinxian Liu, Jinqiang Kuang, Yu Liu, Yuli Wang, Qiong Yu, Weiming Yuan, Suhua Li, Bo Chen, Jiajia Cheng, Baoqiang Wan, Juntao Ye, Shichao Yu