Patents by Inventor Qisong Lin
Qisong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103749Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
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Patent number: 11915785Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.Type: GrantFiled: January 26, 2021Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Lei Zhou, Jung Sheng Hoei, Kishore Kumar Muchherla, Qisong Lin
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Patent number: 11868639Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.Type: GrantFiled: June 17, 2021Date of Patent: January 9, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
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Patent number: 11868202Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.Type: GrantFiled: September 16, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Qisong Lin, Vamsi Pavan Rayaprolu, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Shao Chun Shi
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Patent number: 11847065Abstract: A request to perform a program operation at a memory device is received. Whether a firmware block record is to be modified to correspond with a device block record is determined based on parameters associated with the program operation. The firmware block record tracks entries of the device block record. Responsive to determining that the firmware block record is to be modified, the firmware block record is modified to correspond with the device block record.Type: GrantFiled: August 24, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Mark Ish, Peng Xu
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Patent number: 11798601Abstract: A programmable memory device includes a ROM block to store instructions associated with functionality of the programmable memory device, a memory array having reserved pages to store updates to be performed on the ROM block, and a controller coupled to the ROM block and the memory array. The controller is to, in response to receipt of a remote command from a vendor server via a host system, execute the instructions to perform operations including: executing a set features command to access the set of reserved pages, as an extension to one time programmable mode; programming a set of sub-feature parameters to a specified feature address of the reserved pages, where the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and programming a REM-profiled page of the reserved pages with REM data received from the vendor server via the host system.Type: GrantFiled: December 2, 2021Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Jonathan Wen Jian Oh, Allison Jayne Olson, Fulvio Rori, Qisong Lin, Preston A. Thomson
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Patent number: 11789738Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.Type: GrantFiled: November 14, 2022Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Scott Anthony Stoller, Douglas Eugene Majerus, Qisong Lin
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Publication number: 20230317120Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.Type: ApplicationFiled: December 22, 2020Publication date: October 5, 2023Inventors: Shuai Xu, Michele Piccardi, Arvind Muralidharan, June Lee, Qisong Lin, Scott A. Stoller, Jun Shen
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Publication number: 20230297511Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.Type: ApplicationFiled: March 21, 2023Publication date: September 21, 2023Inventors: Jiangang Wu, Qisong Lin, Jung Sheng Hoei, Yunqiu Wan, Ashutosh Malshe, Peng-Cheng Chen
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Patent number: 11763895Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.Type: GrantFiled: July 26, 2022Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Qisong Lin, Shuai Xu, Jonathan S. Parry, Jeremy Binfet, Michele Piccardi, Qing Liang
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Patent number: 11749362Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.Type: GrantFiled: April 21, 2022Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventors: Scott Anthony Stoller, Kevin R Brandt, Qisong Lin
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Patent number: 11720286Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.Type: GrantFiled: November 1, 2021Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
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Patent number: 11710527Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.Type: GrantFiled: July 19, 2022Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
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Publication number: 20230230624Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.Type: ApplicationFiled: January 26, 2021Publication date: July 20, 2023Inventors: Jiangang Wu, Lei Zhou, Jung Sheng Hoei, Kishore Kumar Muchherla, Qisong Lin
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Patent number: 11704179Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.Type: GrantFiled: October 29, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Harish R. Singidi, Ashutosh Malshe, Sampath K. Ratnam, Qisong Lin, Kishore Kumar Muchherla
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Patent number: 11698864Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.Type: GrantFiled: May 25, 2022Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Abdelhakim Alhussien, Jiangang Wu, Karl D. Schuh, Qisong Lin, Jung Sheng Hoei
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Patent number: 11693774Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.Type: GrantFiled: August 25, 2021Date of Patent: July 4, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Jiangang Wu, Jing Sang Liu, Jung Sheng Hoei, Kishore Kumar Muchherla, Mark Ish, Myoung Jun Go, Nolan Tran, Qisong Lin
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Patent number: 11615029Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.Type: GrantFiled: December 30, 2019Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Qisong Lin, Jung Sheng Hoei, Yunqiu Wan, Ashutosh Malshe, Peng-Cheng Chen
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Publication number: 20230073018Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Inventors: Scott Anthony Stoller, Douglas Eugene Majerus, Qisong Lin
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Publication number: 20230065231Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.Type: ApplicationFiled: August 25, 2021Publication date: March 2, 2023Inventors: Jiangang Wu, Jing Sang Liu, Jung Sheng Hoei, Kishore Kumar Muchherla, Mark Ish, Myoung Jun Go, Nolan Tran, Qisong Lin