Patents by Inventor Qisong Lin
Qisong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230012978Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.Type: ApplicationFiled: September 16, 2022Publication date: January 19, 2023Inventors: Qisong LIN, Vamsi Pavan RAYAPROLU, Jiangang WU, Sampath K. RATNAM, Sivagnanam PARTHASARATHY, Shao Chun SHI
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Publication number: 20230019189Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
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Publication number: 20230017388Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.Type: ApplicationFiled: July 26, 2022Publication date: January 19, 2023Inventors: Qisong Lin, Shuai Xu, Jonathan S. Parry, Jeremy Binfet, Micheie Piccardi, Qing Liang
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Patent number: 11500637Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.Type: GrantFiled: June 15, 2020Date of Patent: November 15, 2022Assignee: Micron Technology, Inc.Inventors: Scott Anthony Stoller, Douglas Eugene Majerus, Qisong Lin
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Publication number: 20220351786Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
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Patent number: 11461158Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write flag bits within a group of memory cells programmed by the multi-pass programming command A processing device, operatively coupled to the memory component, is to perform multi-pass programming of the group of memory cells in association with a logical address. Upon receipt of a read request, the processing device is to determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address of the group of memory cells. The processing device is further to determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error.Type: GrantFiled: August 22, 2019Date of Patent: October 4, 2022Assignee: Micron Technology, Inc.Inventors: Qisong Lin, Vamsi Pavan Rayaprolu, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Shao Chun Shi
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Patent number: 11455109Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.Type: GrantFiled: January 27, 2021Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
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Publication number: 20220283952Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Inventors: Abdelhakim Alhussien, Jiangang Wu, Karl D. Schuh, Qisong Lin, Jung Sheng Hoei
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Publication number: 20220254418Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.Type: ApplicationFiled: February 5, 2021Publication date: August 11, 2022Inventors: Qisong Lin, Shuai Xu, Jonathan S. Parry, Jeremy Binfet, Michele Piccardi, Qing Liang
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Publication number: 20220246222Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.Type: ApplicationFiled: April 21, 2022Publication date: August 4, 2022Inventors: Scott Anthony Stoller, Kevin R. Brandt, Qisong Lin
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Patent number: 11404129Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.Type: GrantFiled: February 5, 2021Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Qisong Lin, Shuai Xu, Jonathan S. Parry, Jeremy Binfet, Michele Piccardi, Qing Liang
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Publication number: 20220236871Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.Type: ApplicationFiled: January 27, 2021Publication date: July 28, 2022Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
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Patent number: 11393541Abstract: A determination that a programming operation has been performed on a memory cell can be made. An amount of time that has elapsed since the programming operation has been performed on the memory cell can be identified. A determination as to whether the amount of time that has elapsed satisfies a threshold time condition can be made. In response to determining that the amount of time that has elapsed satisfies the threshold time condition an operation can be performed on the memory cell to change or maintain a voltage condition of the memory cell.Type: GrantFiled: December 21, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
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Patent number: 11366760Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.Type: GrantFiled: March 12, 2020Date of Patent: June 21, 2022Assignee: Micron Technology, Inc.Inventors: Abdelhakim Alhussien, Jiangang Wu, Karl D. Schuh, Qisong Lin, Jung Sheng Hoei
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Patent number: 11348650Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.Type: GrantFiled: July 14, 2020Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventors: Scott Anthony Stoller, Kevin R Brandt, Qisong Lin
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Publication number: 20220129204Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.Type: ApplicationFiled: November 1, 2021Publication date: April 28, 2022Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
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Publication number: 20220093145Abstract: A programmable memory device includes a ROM block to store instructions associated with functionality of the programmable memory device, a memory array having reserved pages to store updates to be performed on the ROM block, and a controller coupled to the ROM block and the memory array. The controller is to, in response to receipt of a remote command from a vendor server via a host system, execute the instructions to perform operations including: executing a set features command to access the set of reserved pages, as an extension to one time programmable mode; programming a set of sub-feature parameters to a specified feature address of the reserved pages, where the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and programming a REM-profiled page of the reserved pages with REM data received from the vendor server via the host system.Type: ApplicationFiled: December 2, 2021Publication date: March 24, 2022Inventors: Jonathan Wen Jian Oh, Aaron James Olson, Fulvio Rori, Qisong Lin, Preston A. Thomson
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Publication number: 20220050735Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.Type: ApplicationFiled: October 29, 2021Publication date: February 17, 2022Inventors: Vamsi Pavan Rayaprolu, Harish R. Singidi, Ashutosh Malshe, Sampath K. Ratnam, Qisong Lin, Kishore Kumar Muchherla
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Publication number: 20220020439Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.Type: ApplicationFiled: July 14, 2020Publication date: January 20, 2022Inventors: Scott Anthony Stoller, Kevin R. Brandt, Qisong Lin
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Publication number: 20210397509Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write flag bits within a group of memory cells programmed by the multi-pass programming command A processing device, operatively coupled to the memory component, is to perform multi-pass programming of the group of memory cells in association with a logical address. Upon receipt of a read request, the processing device is to determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address of the group of memory cells. The processing device is further to determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error.Type: ApplicationFiled: August 22, 2019Publication date: December 23, 2021Inventors: Qisong Lin, Vamsi Pavan Rayaprolu, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Sho Chun Shi