Patents by Inventor Qiuling Zhu

Qiuling Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210004232
    Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
    Type: Application
    Filed: August 24, 2020
    Publication date: January 7, 2021
    Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
  • Patent number: 10872393
    Abstract: A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 22, 2020
    Assignee: Google LLC
    Inventors: Jason Redgrave, Albert Meixner, Qiuling Zhu, Ji Kim, Artem Vasilyev, Ofer Shacham
  • Patent number: 10791284
    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Google LLC
    Inventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
  • Publication number: 20200275040
    Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 27, 2020
    Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
  • Patent number: 10754654
    Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 25, 2020
    Assignee: Google LLC
    Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
  • Patent number: 10719905
    Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 21, 2020
    Assignee: Google LLC
    Inventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward Chang, William R. Mark
  • Patent number: 10685422
    Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 16, 2020
    Assignee: Google LLC
    Inventors: Albert Meixner, Hyunchul Park, Qiuling Zhu, Jason Rupert Redgrave
  • Patent number: 10685423
    Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 16, 2020
    Assignee: Google LLC
    Inventors: Hyunchul Park, Albert Meixner, Qiuling Zhu, William Mark
  • Publication number: 20200186667
    Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 11, 2020
    Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein
  • Patent number: 10638073
    Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 28, 2020
    Assignee: Google LLC
    Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
  • Publication number: 20200120287
    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 16, 2020
    Inventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
  • Publication number: 20200098083
    Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.
    Type: Application
    Filed: September 27, 2019
    Publication date: March 26, 2020
    Inventors: Hyunchul Park, Albert Meixner, Qiuling Zhu, William Mark
  • Patent number: 10560598
    Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 11, 2020
    Assignee: Google LLC
    Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein
  • Patent number: 10516833
    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: December 24, 2019
    Assignee: Google LLC
    Inventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
  • Publication number: 20190378239
    Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward Chang, William R. Mark
  • Publication number: 20190364174
    Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 28, 2019
    Inventors: Ofer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark
  • Publication number: 20190327433
    Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
    Type: Application
    Filed: May 3, 2019
    Publication date: October 24, 2019
    Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
  • Patent number: 10430919
    Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: October 1, 2019
    Assignee: Google LLC
    Inventors: Hyunchul Park, Albert Meixner, Qiuling Zhu, William Mark
  • Patent number: 10417732
    Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: September 17, 2019
    Assignee: Google LLC
    Inventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward Chang, William Mark
  • Patent number: 10397450
    Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 27, 2019
    Assignee: Google LLC
    Inventors: Ofer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark