Patents by Inventor Qiuling Zhu
Qiuling Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11190718Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.Type: GrantFiled: April 27, 2020Date of Patent: November 30, 2021Assignee: Google LLCInventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
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Patent number: 11153464Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.Type: GrantFiled: July 30, 2019Date of Patent: October 19, 2021Assignee: Google LLCInventors: Ofer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark
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Patent number: 11140293Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.Type: GrantFiled: February 10, 2020Date of Patent: October 5, 2021Assignee: Google LLCInventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein
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Patent number: 11138013Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.Type: GrantFiled: August 24, 2020Date of Patent: October 5, 2021Assignee: Google LLCInventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
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Publication number: 20210004232Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.Type: ApplicationFiled: August 24, 2020Publication date: January 7, 2021Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
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Patent number: 10872393Abstract: A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.Type: GrantFiled: May 15, 2017Date of Patent: December 22, 2020Assignee: Google LLCInventors: Jason Redgrave, Albert Meixner, Qiuling Zhu, Ji Kim, Artem Vasilyev, Ofer Shacham
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Patent number: 10791284Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.Type: GrantFiled: October 22, 2019Date of Patent: September 29, 2020Assignee: Google LLCInventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
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Publication number: 20200275040Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.Type: ApplicationFiled: April 27, 2020Publication date: August 27, 2020Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
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Patent number: 10754654Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.Type: GrantFiled: March 28, 2019Date of Patent: August 25, 2020Assignee: Google LLCInventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
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Patent number: 10719905Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.Type: GrantFiled: August 22, 2019Date of Patent: July 21, 2020Assignee: Google LLCInventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward Chang, William R. Mark
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Patent number: 10685423Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.Type: GrantFiled: September 27, 2019Date of Patent: June 16, 2020Assignee: Google LLCInventors: Hyunchul Park, Albert Meixner, Qiuling Zhu, William Mark
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Patent number: 10685422Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.Type: GrantFiled: February 11, 2019Date of Patent: June 16, 2020Assignee: Google LLCInventors: Albert Meixner, Hyunchul Park, Qiuling Zhu, Jason Rupert Redgrave
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Publication number: 20200186667Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.Type: ApplicationFiled: February 10, 2020Publication date: June 11, 2020Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein
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Patent number: 10638073Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.Type: GrantFiled: May 3, 2019Date of Patent: April 28, 2020Assignee: Google LLCInventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
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Publication number: 20200120287Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.Type: ApplicationFiled: October 22, 2019Publication date: April 16, 2020Inventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
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Publication number: 20200098083Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.Type: ApplicationFiled: September 27, 2019Publication date: March 26, 2020Inventors: Hyunchul Park, Albert Meixner, Qiuling Zhu, William Mark
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Patent number: 10560598Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.Type: GrantFiled: March 4, 2019Date of Patent: February 11, 2020Assignee: Google LLCInventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein
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Patent number: 10516833Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.Type: GrantFiled: April 5, 2019Date of Patent: December 24, 2019Assignee: Google LLCInventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
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Publication number: 20190378239Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.Type: ApplicationFiled: August 22, 2019Publication date: December 12, 2019Inventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward Chang, William R. Mark
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Publication number: 20190364174Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.Type: ApplicationFiled: July 30, 2019Publication date: November 28, 2019Inventors: Ofer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark