Abstract: A non-volatile memory including a substrate, a charge storage structure, two metal gate structures, a first dielectric layer, a second dielectric layer, a first doped region and a second doped region is provided. The charge storage structure is disposed on the substrate. The metal gate structures are disposed on the substrate at two sides of the charge storage structure. The first dielectric layer is disposed between the charge storage structure and the metal gate structures. The second dielectric layer is disposed between the charge storage structure and the substrate. The first doped region and the second doped region are disposed in the substrate at sides of the metal gate structures away from the charge storage structure.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.

Abstract: A non-volatile memory including a substrate, a charge storage structure, two metal gate structures, a first dielectric layer, a second dielectric layer, a first doped region and a second doped region is provided. The charge storage structure is disposed on the substrate. The metal gate structures are disposed on the substrate at two sides of the charge storage structure. The first dielectric layer is disposed between the charge storage structure and the metal gate structures. The second dielectric layer is disposed between the charge storage structure and the substrate. The first doped region and the second doped region are disposed in the substrate at sides of the metal gate structures away from the charge storage structure.

Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.

Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.

Abstract: A semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.

Abstract: A display assembly includes a front frame with an opening, a display panel, and a back frame. The display panel is mounted between the front frame and the back frame. The front frame includes a front frame body and a side frame portion surrounding the front frame body. A groove is defined in the side frame portion. The back frame includes a receiving portion and a mounting portion. The mounting portion includes an outer frame body surrounding the receiving portion and one or more flanges protruding from the outer frame body. The receiving portion defines a receiving section for receiving the display panel. The back frame includes one or more resisting blocks protruding from the receiving section. The resisting blocks resist the display panel. The flanges engage in the groove to secure the front frame to the back frame.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

Abstract: An electronic billboard includes a base, bracket, a display and a touch device. The bracket is removable and mounted to the base. The display is removable and mounted to the bracket. The display includes a slot and a receiving portion configured to receive a host. The touch device is received in the slot.

Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.

Abstract: A display apparatus includes a display body, an operation member with an operation portion and a mounting portion, a bracket, and a gripping member. The operation member is slidably mounted on the inside of the bracket. The bracket includes a bracket body and a receiving member with a resisting portion. The gripping member is movably received in the receiving member and includes a gripping body, a pressing portion, and two or mover gripping arms. The mounting portion is positioned between the gripping arms positioning the operation member within the bracket body allowing the operation portion to drive the mounting member and the gripping member to slide. The pressing portion resists the resisting portion so that the gripping arms may be spread to disengage from the mounting portion.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure. Preferably, the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn.

Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.

Abstract: A display device includes a front side and a rear side. A screen is mounted on the front side. A stand is mounted on the rear side. The stand includes a first supporting piece and a second supporting piece obtusely connected to the first supporting piece. The first supporting piece is pivotably connected to the rear side of the display device. A circuit board is mounted on the first supporting piece of the stand.

Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.