Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, ?. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various ? values.

Abstract: A system and method are disclosed to utilize Gray code in order to reduce the power consumption of column drivers in a display system. Binary source data is received from a timing controller. A Gray code digitizer converts and encodes the binary source data into a binary portion of data and a Gray code data. The binary portion data and the Gray code data are transmitted through a shift register to a digital-to-analog converter. The shift register consumes less power processing the converted binary portion of data and Gray code data than the corresponding binary source data. The digital-to-analog converter decodes the Gray code and generates corresponding gamma voltage levels for display use.

Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, ?. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various ? values.

Abstract: A new method of ortho-fluorination for selectively fluorinating a benzoic acid or derivative compound where an aryl C—H bond is directly replaced by an aryl C—F bond is provided. The method comprises reacting a compound having the formula: wherein X is at least one substitution group attached with a benzene ring and Ar is an aromatic substitution group comprising at least one fluorine atom, and a mixture comprising a palladium (II) catalyst and a fluorinating reagent to form at least one of the ortho-fluorinated compounds having the formulae with good yield and selectivity.

Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, ?. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various ? values.

Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

Abstract: A new method of ortho-fluorination where an aryl C—H bond is directly replaced by an aryl C-F bond in a palladium-catalyzed reaction is provided. The method includes the ortho-fluorination of a triflamide protected benzylamine, a palladium catalyst, such as Pd(OTf)2, a fluorinating reagent such as N-fluoro-2,4,6-trimethylpyridinium triflate, and a ligand to promote the reaction such as N-methylpyrrolidinone (NMP).

Abstract: A method for multi-path TDM data transmission includes: applying a plurality of high-speed serial lines to connect a center switch network board to a plurality of service boards; multiplexing multi-path TDM data from the center switch network board at transmitting side, and transmitting TDM data multiplexed in batch via one of the high-speed serial lines to one of the service boards; at receiving side, serial receiving the TDM data multiplexed and de-multiplexing the TDM data multiplexed to multiple TDM paths. The TDM bridge connector includes: a TDM high-speed serial transmitting adaptive circuit, and a TDM high-speed serial receiving adaptive circuit and a clock control circuit. The invention increases greatly transmission capacity and looses the requirement of clock synchronization, so the system reliability is greatly raised.

Abstract: A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. The resistor network further includes a servo resistor in series with a servo resistor switch such that the servo resistor and servo resistor switch are in parallel with the plurality of resistor and switch pairs. The servo loop generates a shift register gating signal and includes a current sample register for storing a current comparator output data value and a previous sample register for storing a previous comparator output data value. The shift register, upon receipt of a shift register gating signal at a first state, inputs the current comparator output data value to shift data bits through the shift register.

Abstract: A current mode logic circuit includes a current mode logic driver circuit and a transistor biasing improvement circuit. The transistor biasing improvement circuit includes a first current source coupled to a first output node of the current mode logic driver circuit and a second current source coupled to a second output node of the current mode logic driver circuit. The first current source and the second current source raise a common mode voltage at the first output node and the second output node.

Abstract: An actively compensated CML circuit includes a CML buffer circuit and a bandwidth expansion circuit. The CML buffer circuit includes a first MOS transistor and a second MOS transistor in a differential pair configuration. A first load resistor is coupled to a first MOS transistor drain at a first output terminal and a second load resistor is coupled to a second MOS transistor drain at a second output terminal. The bandwidth expansion circuit is coupled to the CML buffer circuit in a source follower configuration. The bandwidth expansion circuit includes a third MOS transistor and a fourth MOS transistor. A capacitor is coupled across a third MOS transistor source and a fourth MOS transistor source. The fourth MOS transistor and the third MOS transistor generate a high pass function at the first output terminal and the second output terminal.

Abstract: Systems and methods for on-chip resistor calibration are disclosed. A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. The resistor network further includes a servo resistor in series with a servo resistor switch such that the servo resistor and servo resistor switch are in parallel with the plurality of resistor and switch pairs. The servo loop generates a shift register gating signal and includes a current sample register for storing a current comparator output data value and a previous sample register for storing a previous comparator output data value. The shift register, upon receipt of a shift register gating signal at a first state, inputs the current comparator output data value to shift data bits through the shift register.

Abstract: A new and improved lift mechanism which is suitably adapted for raising and lowering a pedestal/heater assembly inside a processing chamber for semiconductor wafer substrates. The pedestal/heater assembly lift mechanism includes a drive motor which is directly coupled through a shaft coupling to a threaded lead screw for rotating the lead screw in the clockwise or counterclockwise direction. The lead screw threadibly engages the pedestal/heater assembly for selectively raising and lowering the pedestal/heater assembly inside the processing chamber.

Abstract: The invention discloses a method for multi-path TDM data transmission based on backplane and a TDM bridge connector for implementing the method. The method includes: applying a high-speed serial line on backplane to connect a center switch network board and service boards; multiplexing or interleaving multi-path TDM data at transmitting side, and then transmitting in batch to said high-speed serial line on the backplane; at receiving side, serial receiving said data and de-multiplexing or de-interleaving them to multiple TDM paths. The TDM bridge connector includes: a TDM high-speed serial transmitting adaptive circuit, a TDM high-speed serial receiving adaptive circuit and a clock control circuit. The invention increases greatly transmission capacity on backplane and looses the requirement of clock synchronization, so the system reliability is greatly raised.

Abstract: A bandgap reference circuit that operates with a voltage supply that can be less than 1 volt and that has one stable, non-zero current operating point. The core has a current generator embedded within it and includes one operational amplifier that provides a self-regulated voltage for several transistors used in the circuit.

Abstract: A bandgap reference circuit that operates with a voltage supply that can be lass than 1 volt and that has one stable, non-zero current operating point.

Abstract: An electrically conducting fuel filter mechanism for a fuel supply system for an internal combustion engine. The housing for the fuel filter has a conductive inner or core layer and at least one non-conductive outer layer positioned adjacent the fuel. The conductive layer is made from a non-conductive material with conductive fibers or powders mixed in it, while the non-conductive layer is free from the conductive materials. Any electrostatic or electrical charge buildup in the fuel filter, fuel or housing, will be dissipated through the inner non-conductive layer forming conductive paths directly to the conductive layer. This prevents any further charge buildup and pitting.

Abstract: An electrically conducting fuel filter mechanism for a fuel supply system for an internal combustion engine. The housing for the fuel filter has a conductive inner or core layer and at least one non-conductive outer layer positioned adjacent the fuel. The conductive layer is made from a non-conductive material with conductive fibers or powders mixed in it, while the non-conductive layer is free from the conductive materials. Any electrostatic or electrical charge buildup in the fuel filter, fuel or housing, will be dissipated through the inner non-conductive layer forming conductive paths directly to the conductive layer. This prevents any further charge buildup and pitting.