Abstract: A method of quantifying the coverage of extra particulate additives (EPA) on the surface of toner particles is provided. More specifically, this invention is a method using automated image analysis to correctly identify toner and coverage of EPA particles on the surface of the toner.

Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region.

Abstract: A flue gas treatment apparatus has a flue gas inlet, a treated gas outlet downstream of the flue gas inlet, and a gas flow path therebetween. The flue gas treatment apparatus comprises a particulate removal device. A first heater is downstream of the particulate removal device. The first heater heats the flue gas to a first treatment temperature. A first catalytic converter is downstream of the first heater for eliminating at least some CO and SO2 from the flue gas. A second heater is downstream of the first catalytic converter for heating the flue gas to a second treatment temperature. A second catalytic converter is downstream of the second heater for eliminating at least some NOx from the flue gas. At least a first fan forces the flue gas from the flue gas inlet to the treated gas outlet.

Abstract: Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.

Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

Abstract: A processing method supporting out-of-order execution (OOE) includes load-hit-store (LHS) hazard prediction at the instruction execution phase, reducing load instruction rejections and queue flushes at the dispatch phase. The instruction dispatch unit (IDU) detects likely LHS hazards by generating entries for pending stores in a LHS detection table. The entries in the table contain an address field (generally the immediate field) of the store instruction and the register number of the store. The ISU compares the address field and register number for each load with entries in the table to determine if a likely LHS hazard exists and if an LHS hazard is detected, the load is dispatched to the issue queue of the load-store unit (LSU) with a tag corresponding to the matching store instruction, causing the LSU to dispatch the load only after the corresponding store has been dispatched for execution.

Abstract: A processor core supporting out-of-order execution (OOE) includes load-hit-store (LHS) hazard prediction at the instruction execution phase, reducing load instruction rejections and queue flushes at the dispatch phase. The instruction dispatch unit (IDU) detects likely LHS hazards by generating entries for pending stores in a LHS detection table. The entries in the table contain an address field (generally the immediate field) of the store instruction and the register number of the store. The ISU compares the address field and register number for each load with entries in the table to determine if a likely LHS hazard exists and if an LHS hazard is detected, the load is dispatched to the issue queue of the load-store unit (LSU) with a tag corresponding to the matching store instruction, causing the LSU to dispatch the load only after the corresponding store has been dispatched for execution.

Abstract: Reject code handling is utilized for a more time-efficient selection of data-capable networks.

Abstract: The invention relates to a DNA sequence, which codes for a polypeptide having phospholipase activity essentially without lipase activity, characterized in that the DNA sequence is selected from a) DNA sequences that comprise a nucleotide sequence according to SEQ ID NO: 1, b) DNA sequences that comprise the coding sequence according to SEQ ID NO: 1, c) DNA sequences that code for the protein sequence according to SEQ ID NO: 2, d) DNA sequences that are coded for by the plasmid pPL3940-Topo2.5 with the restriction map according to FIG.

Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage.

Abstract: The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.

Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

Abstract: The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.

Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed.

Abstract: Subsets of isolated communications networks are selectively merged without merging the entire isolated communications networks, and devices are imported across isolated communications networks without merging the isolated communications networks. The presently disclosed technology provides for improved scalability, performance, and security in logical networks spanning two or more physical communications networks.

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

Abstract: The invention relates to a DNA sequence, which codes for a polypeptide having phospholipase activity essentially without lipase activity, characterized in that the DNA sequence is selected from a) DNA sequences that comprise a nucleotide sequence according to SEQ ID NO: 1, b) DNA sequences that comprise the coding sequence according to SEQ ID NO: 1, c) DNA sequences that code for the protein sequence according to SEQ ID NO: 2, d) DNA sequences that are coded for by the plasmid pPL3940-Topo2.5 with the restriction map according to FIG.

Abstract: Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.

Abstract: A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.