Patents by Inventor Qwan Ho Chung
Qwan Ho Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130334683Abstract: An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.Type: ApplicationFiled: September 14, 2012Publication date: December 19, 2013Applicant: SK HYNIX INC.Inventors: Seung Jee KIM, Qwan Ho CHUNG, Jong Hyun NAM, Si Han KIM, Sang Yong LEE, Seong Cheol SHIN
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Publication number: 20130334685Abstract: An embedded package that may be realized by surrounding a semiconductor chip (or a semiconductor die) in a package substrate. A semiconductor chip of an embedded package may be electrically connected to external connection terminals through interconnection wires instead of bumps, and the interconnection wires may be formed using a wire bonding process. A high reliability embedded package results.Type: ApplicationFiled: September 13, 2012Publication date: December 19, 2013Applicant: SK HYNIX INC.Inventors: Si Han KIM, Qwan Ho CHUNG, Seung Jee KIM, Jong Hyun NAM, Sang Yong LEE
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Publication number: 20130236993Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: ApplicationFiled: April 24, 2013Publication date: September 12, 2013Applicant: SK HYNIX INC.Inventors: Woong Sun LEE, Qwan Ho CHUNG
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Patent number: 8461696Abstract: A substrate for a semiconductor package is provided having first and second core layers defining a cavity having an adhesive member and sized and shaped to receive a semiconductor chip. The semiconductor package further having a connection member formed on a bond finger and connected to a via pattern formed through the first and second core layers. A stack package is also provided having multiple substrates.Type: GrantFiled: December 28, 2009Date of Patent: June 11, 2013Assignee: Hynix Semiconductor Inc.Inventors: Kyu Won Lee, Qwan Ho Chung
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Patent number: 8445322Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: GrantFiled: September 23, 2011Date of Patent: May 21, 2013Assignee: SK Hynix Inc.Inventors: Woong Sun Lee, Qwan Ho Chung
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Patent number: 8441116Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.Type: GrantFiled: May 7, 2012Date of Patent: May 14, 2013Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Qwan Ho Chung, Il Hwan Cho, Sang Joon Lim, Jong Woo Yoo, Jin Ho Bae, Seung Hyun Lee
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Patent number: 8399294Abstract: A semiconductor package for quickly discharging heat and a method for fabricating the same are disclosed. The semiconductor package includes a semiconductor package module having a first insulation member and at least one fluid passage passing through the insulation member. Circuit patterns are formed on a first face of the first insulation member. Semiconductor chips are then disposed on the first face and are electrically connected with the circuit patterns respectively. A second insulation member is formed so as to surround the side faces of the semiconductor chips, the first insulation member, and the circuit patterns. Finally, a through electrode is formed passing through the second insulation member of the semiconductor package module and electrically connecting to the circuit patterns.Type: GrantFiled: August 13, 2012Date of Patent: March 19, 2013Assignee: Hynix Semiconductor Inc.Inventor: Qwan Ho Chung
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Publication number: 20130037938Abstract: An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to is the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump.Type: ApplicationFiled: December 22, 2011Publication date: February 14, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Qwan Ho CHUNG
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Patent number: 8343803Abstract: A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections.Type: GrantFiled: October 27, 2010Date of Patent: January 1, 2013Assignee: Hynix Semiconductor Inc.Inventor: Qwan Ho Chung
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Publication number: 20120309129Abstract: A semiconductor package for quickly discharging heat and a method for fabricating the same are disclosed. The semiconductor package includes a semiconductor package module having a first insulation member and at least one fluid passage passing through the insulation member. Circuit patterns are formed on a first face of the first insulation member. Semiconductor chips are then disposed on the first face and are electrically connected with the circuit patterns respectively. A second insulation member is formed so as to surround the side faces of the semiconductor chips, the first insulation member, and the circuit patterns. Finally, a through electrode is formed passing through the second insulation member of the semiconductor package module and electrically connecting to the circuit patterns.Type: ApplicationFiled: August 13, 2012Publication date: December 6, 2012Inventor: Qwan Ho CHUNG
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Patent number: 8264087Abstract: A semiconductor package for quickly discharging heat and a method for fabricating the same are disclosed. The semiconductor package includes a semiconductor package module having a first insulation member and at least one fluid passage passing through the insulation member. Circuit patterns are formed on a first face of the first insulation member. Semiconductor chips are then disposed on the first face and are electrically connected with the circuit patterns respectively. A second insulation member is formed so as to surround the side faces of the semiconductor chips, the first insulation member, and the circuit patterns. Finally, a through electrode is formed passing through the second insulation member of the semiconductor package module and electrically connecting to the circuit patterns.Type: GrantFiled: April 30, 2009Date of Patent: September 11, 2012Assignee: Hynix Semiconductor Inc.Inventor: Qwan Ho Chung
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Publication number: 20120217637Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.Type: ApplicationFiled: May 7, 2012Publication date: August 30, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Woong Sun LEE, Qwan Ho CHUNG, Il Hwan CHO, Sang Joon LIM, Jong Woo YOO, Jin Ho BAE, Seung Hyun LEE
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Publication number: 20120208325Abstract: Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a base substrate. A heat pressure process is performed to form a wiring support member on the base substrate to cover the top surface and the side surfaces of the semiconductor chip while exposing each of the bumps. Wirings are formed to be electrically connected to the bumps on the wiring support member. The base substrate is removed from the semiconductor chip and the wiring support member.Type: ApplicationFiled: April 25, 2012Publication date: August 16, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Qwan Ho CHUNG
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Publication number: 20120112342Abstract: A semiconductor device includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first electrode pads on the first surface, a stress buffer layer formed on the first electrode pads and the first surface of the first structural body, and having a plurality of holes which expose the first electrode pads, and a plurality of bumps formed to be electrically connected with the first electrode pads through the plurality of holes, wherein the plurality of bumps include first bumps which are filled in corresponding holes of the plurality of holes and second bumps which are formed on the first bumps and the stress buffer layer and are disposed over the first electrode pads and portions of the first surface outside the first electrode pads.Type: ApplicationFiled: September 23, 2011Publication date: May 10, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Sung Ho HYUN, Qwan Ho CHUNG, Myung Gun PARK
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BUMP FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE HAVING BUMP, AND STACKED SEMICONDUCTOR PACKAGE
Publication number: 20120091584Abstract: A bump for a semiconductor package includes: a first bump formed on a semiconductor chip and having at least two land parts and a connection part which connects the land parts and has a line width smaller than the land parts; and a second bump formed on the first bump and projecting on the land parts of the first bump in shapes of a hemisphere.Type: ApplicationFiled: December 29, 2010Publication date: April 19, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Ki Young KIM, Qwan Ho CHUNG, Sung Ho HYUN, Myung Gun PARK, Jin Ho BAE -
Patent number: 8129627Abstract: A circuit board includes a semiconductor chip having an upper surface and side surfaces connected to the upper surface. A bonding pad is disposed on the upper surface of the semiconductor chip. A bump is disposed on the bonding pad and projects from the bonding pad by a predetermined height. A circuit board body has a recess part, and the semiconductor chip is positioned in the recess part so that the circuit board body covers the upper surface and the side surfaces of the semiconductor chip while exposing an end of the bump. A wiring line is disposed on the circuit board body and part of the wiring line is positioned over the bump. An opening is formed in a portion of the part of the wiring line over the bump to expose the bump. A reinforcing member physically and electrically connects the exposed bump and the wiring line.Type: GrantFiled: October 23, 2009Date of Patent: March 6, 2012Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Qwan Ho Chung, Ki Young Kim
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Publication number: 20120015477Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Inventors: Woong Sun LEE, Qwan Ho CHUNG
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Publication number: 20110309504Abstract: A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.Type: ApplicationFiled: May 31, 2011Publication date: December 22, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jin Ho BAE, Qwan Ho CHUNG, Woong Sun LEE
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Patent number: 8053879Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: GrantFiled: October 30, 2008Date of Patent: November 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Qwan Ho Chung
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Patent number: 8030739Abstract: A stacked semiconductor package includes a plurality of stacked semiconductor chips each having a circuit unit, a data pad, and a chip selection pad. The plurality of stacked semiconductor chips also includes a plurality of chip selection through electrodes. The chip selection through electrodes penetrate the chip selection pads and the semiconductor chips, and the chip selection through electrodes receive chip selection signals. The chip selection pad of a semiconductor chip is electrically connected to the chip selection through electrode that receives the chip selection signal for selecting the semiconductor chip. The chip selection pad is electrically insulated from the chip selection through electrodes for receiving the chip selection signal for selecting a different semiconductor chip.Type: GrantFiled: October 29, 2008Date of Patent: October 4, 2011Assignee: Hynix Semiconductor Inc.Inventor: Qwan Ho Chung