Abstract: A stacked semiconductor package includes a semiconductor package module in which a plurality of semiconductor packages, which include a substrate and a semiconductor chip mounted over the substrate, are stacked. The stacked semiconductor package includes connectors for electrically connecting pairs of adjacent semiconductor packages so as to provide sequentially a signal from a lower semiconductor package of the semiconductor package module toward an upper semiconductor package.

Abstract: The semiconductor package includes a semiconductor package module with circuit patterns formed on an insulation substrate, at least two semiconductor chips electrically connected to each of the circuit patterns using bumps, and an insulation member filled in any open space in the semiconductor module. A cover plate is formed on the upper portion of the semiconductor package module, and a penetration electrode penetrates the semiconductor package. The penetration electrode is electrically connected to the circuit patterns. The described semiconductor package improves upon important characteristics such as size, reliability, warpage prevention, and heat dissipation.

Abstract: The stacked semiconductor package includes a substrate having a plurality of connection pads; a first semiconductor chip disposed over the substrate, a plurality of first bonding pads disposed at an first of the first semiconductor chip, redistributions extending from the first bonding pads to the middle of the upper face; wires for electrically connecting the first bonding pads to the connection pads; and a second semiconductor chip disposed over the first semiconductor chip leaving the first bonding pads exposed, and a plurality of second bonding pads disposed over the second semiconductor chip body and connected to the redistributions in a flip-chip manner. The stacked semiconductor package with this structure has a decreased volume, thus making the stacked semiconductor package more compact.

Abstract: A stack package and a method for manufacturing the same. The stack package includes first and second semiconductor chips placed such that surfaces thereof, on which bonding pads are formed, face each other; a plurality of through-silicon vias formed in the first and second semiconductor chips; and a plurality of redistribution layers formed on the surfaces of the first and second semiconductor chips to connect the through-silicon vias to the corresponding bonding pad, wherein the redistribution layers of the first and second semiconductor chips contact each other. By forming the stack package in this manner, it is possible to prevent pick-up error and cracks from forming during the manufacturing process, and therefore the stack package can be reliable formed.

Abstract: A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections.

Abstract: A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and an insulation layer covering the first and second areas and having at least one void removing part which extends from the first area to the second area to prevent a void from being formed.

Abstract: Disclosed are a semiconductor chip package and a method for fabricating the same. The semiconductor chip package includes a semiconductor chip and a circuit board. The semiconductor chip is bonded to the circuit board by means of adhesive except for a metal-exposed region of the semiconductor chip. Anti-migration material is formed between the circuit board and a predetermined portion of the semiconductor chip, in which the predetermined portion of the semiconductor chip has no adhesive, in order to prevent material contained in the metal trace from migrating to the metal-exposed region of the semiconductor chip. A lamination phenomenon is not created between the circuit board and the semiconductor chip after the HAST has been carried out.

Abstract: Disclosed are a semiconductor chip package and a method for fabricating the same. The semiconductor chip package includes a semiconductor chip and a circuit board. The semiconductor chip is bonded to the circuit board by means of adhesive except for a metal-exposed region of the semiconductor chip. Anti-migration material is formed between the circuit board and a predetermined portion of the semiconductor chip, in which the predetermined portion of the semiconductor chip has no adhesive, in order to prevent material contained in the metal trace from migrating to the metal-exposed region of the semiconductor chip. A lamination phenomenon is not created between the circuit board and the semiconductor chip after the HAST has been carried out.

Abstract: A wafer level package including a semiconductor chip having a plurality of bonding pads on a front surface thereof; a lower insulation layer formed on the semiconductor chip to expose the bonding pads; re-distribution lines formed on the lower insulation layer to be connected to the bonding pads at first ends thereof; an upper insulation layer formed on the lower insulation layer including the re-distribution lines, with portions of the re-distribution lines exposed; solder balls attached to the exposed portions of the re-distribution lines; and a cap covering a rear surface of the semiconductor chip.

Abstract: Disclosed are a semiconductor chip package and a method for fabricating the same. The semiconductor chip package includes a semiconductor chip and a circuit board. The semiconductor chip is bonded to the circuit board by means of adhesive except for a metal-exposed region of the semiconductor chip. Anti-migration material is formed between the circuit board and a predetermined portion of the semiconductor chip, in which the predetermined portion of the semiconductor chip has no adhesive, in order to prevent material contained in the metal trace from migrating to the metal-exposed region of the semiconductor chip. A lamination phenomenon is not created between the circuit board and the semiconductor chip after the HAST has been carried out.

Abstract: Disclosed are a semiconductor chip package and a method for fabricating the same. The semiconductor chip package includes a semiconductor chip and a circuit board. The semiconductor chip is bonded to the circuit board by means of adhesive except for a metal-exposed region of the semiconductor chip. Anti-migration material is formed between the circuit board and a predetermined portion of the semiconductor chip, in which the predetermined portion of the semiconductor chip has no adhesive, in order to prevent material contained in the metal trace from migrating to the metal-exposed region of the semiconductor chip. A lamination phenomenon is not created between the circuit board and the semiconductor chip after the HAST has been carried out.

Abstract: The present invention discloses a chip-stacked package is disclosed. The chip-stacked package comprises: a doubly down-set leadframe having a down-set tip to be wire-bonded; a first semiconductor chip attached under the down-set tip of the leadframe; a first metal wire electrically connecting bonding pads of the first semiconductor chip with the down-set tip of the leadframe; a second semiconductor chip attached on the leadframe; a second metal wire electrically connecting the second semiconductor chip with the leadframe; and an epoxy molding compound encapsulating the first and second semiconductor chips, the first and second metal wires, and a portion of the leadframe while exposing the backside of the first semiconductor chip. According to the present invention, since the chip-stacked package is manufactured using the general LOC leadframe, a manufacturing process thereof can be simplified as compared to the existing chip-stacked package.