Patents by Inventor R. List

R. List has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210090120
    Abstract: Systems, methods, and computer-readable mediums, consistent with principles of some embodiments of the present invention provide for applying a user interface to an electronic device including storing information relating to a user of an electronic device, wherein the stored information includes user information data and user history data, storing a template user interface, modifying the user interface based on the stored user information and the user history data, and applying the modified user interface to the electronic device, wherein the user interface enables a user to instruct the electronic device to perform operations within a shopping establishment.
    Type: Application
    Filed: October 2, 2020
    Publication date: March 25, 2021
    Applicant: Mercatus Technologies Inc.
    Inventors: R. Sylvain Perrier, Russell Harper, Robin Harrison, Michael Fedorov, Jiang Zhao, Denys Montuzenko, Robert Segal, Harold Springer, Jeremy List, Lucy List
  • Patent number: 10710032
    Abstract: A universal wall and bridge mounted aeration apparatus has a track extending between two distinct elevations that is coupled to a wall and bridge mount. An aeration unit is pivotally coupled to the track and has an aerator adapted to operatively at least partially submerge within and aerate a liquid. A selective mover or drive is adapted to operatively move the aeration unit along the track and thereby vary an elevation of the aeration unit. The universal wall and bridge mount supports the track and aeration unit. The universal wall and bridge mount has a first configuration for mounting to a structure such as a stationary bridge, and a second configuration for mounting to a wall. The universal wall and bridge mounted aeration apparatus may be adjusted to position the propeller after installation under the surface of the liquid through three axes of motion freedom.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 14, 2020
    Assignee: Aeration Industries International, LLC
    Inventors: Randy W. List, Jing Huang, Joseph F. Widman, Brian J. Cohen, Todd M. Schroeder, Gregory R. Harding, Paul P. Gorbunow, Jason L. Jones, Steven R. Carleton
  • Patent number: 7378331
    Abstract: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventors: Mohamad Shaheen, Peter G. Tolchinsky, Irwin Yablok, Scott R. List
  • Publication number: 20070278668
    Abstract: An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.
    Type: Application
    Filed: August 15, 2007
    Publication date: December 6, 2007
    Inventors: Sarah Kim, R. List, James Maveety, Alan Myers, Quat Vu
  • Publication number: 20070200226
    Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.
    Type: Application
    Filed: April 27, 2007
    Publication date: August 30, 2007
    Inventors: Sarah Kim, R. List, Alan Myers
  • Publication number: 20070190695
    Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.
    Type: Application
    Filed: March 26, 2007
    Publication date: August 16, 2007
    Inventors: Alan Myers, R. List, Gilroy Vandentop
  • Publication number: 20070111386
    Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 17, 2007
    Inventors: Sarah Kim, R. List, Scot Kellar
  • Publication number: 20070087528
    Abstract: Method and structure for vertically stacking microelectronic devices are disclosed. Subsequent to appropriate deposition, patterning, trenching, and passivation subprocesses, a conductive layer is formed wherein one end comprises an external contact portion for C4 interfacing, and another end establishes electrical contact with an internal contact at the bonding interface between the two interfaced devices. The conductive layer may be formed using electroplating, and may be formed in a single electroplating treatment, to form a continuous structure from via portion to external contact portion.
    Type: Application
    Filed: December 13, 2006
    Publication date: April 19, 2007
    Inventors: Sarah Kim, R. List
  • Publication number: 20070020805
    Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
    Type: Application
    Filed: September 27, 2006
    Publication date: January 25, 2007
    Inventors: Sarah Kim, R. List, Tom Letson
  • Publication number: 20070015340
    Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.
    Type: Application
    Filed: September 18, 2006
    Publication date: January 18, 2007
    Inventors: Mauro Kobrinsky, R. List, Sarah Kim, Michael Harmes
  • Publication number: 20060226541
    Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.
    Type: Application
    Filed: June 7, 2006
    Publication date: October 12, 2006
    Inventors: Sarah Kim, R. List, James Maveety, Alan Myers, Quat Vu
  • Publication number: 20060097383
    Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.
    Type: Application
    Filed: December 9, 2005
    Publication date: May 11, 2006
    Inventors: Shriram Ramanathan, Sarah Kim, R. List, Gregory Chrysler
  • Publication number: 20060076678
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Application
    Filed: November 16, 2005
    Publication date: April 13, 2006
    Inventors: Sarah Kim, Bob Martell, David Ayers, R. List, Peter Moon, Steven Towle, Anna George
  • Publication number: 20060055030
    Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.
    Type: Application
    Filed: November 9, 2005
    Publication date: March 16, 2006
    Inventors: Sarah Kim, R. List, James Maveety, Alan Myers, Quat Vu, Ravi Prasher, Ravi Mahajan, Gilroy Vandentop
  • Publication number: 20050215056
    Abstract: According to one embodiment a method is disclosed. The method includes applying a photoresist layer to a first wafer, etching the first wafer, bonding the first wafer to a second wafer and thinning the first wafer; wherein an unsupported bevel portion of the first wafer is removed.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 29, 2005
    Inventors: Patrick Morrow, R. List, Michael Chan
  • Publication number: 20050184400
    Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.
    Type: Application
    Filed: February 7, 2005
    Publication date: August 25, 2005
    Inventors: Mauro Kobrinsky, R. List, Sarah Kim, Michael Harmes
  • Publication number: 20050164490
    Abstract: Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.
    Type: Application
    Filed: March 2, 2005
    Publication date: July 28, 2005
    Inventors: Patrick Morrow, R. List, Sarah Kim
  • Publication number: 20050139996
    Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.
    Type: Application
    Filed: December 31, 2003
    Publication date: June 30, 2005
    Inventors: Alan Myers, R. List, Gilroy Vandentop
  • Publication number: 20050112816
    Abstract: A device where the electrodes of an electroosmotic pump are located directly in the flow-producing region of the electroosmotic pump is described as well as methods of forming such a device. Placing the electrodes of an electroosmotic pump directly in the flow-producing region of the electroosmotic pump may increase the flow rate of a cooling fluid that is pumped through the pump. The cooling fluid may then remove a greater amount of heat from the substrate over which it is flowed. The substrate may be the non-device side of a die or a thermal management chip that is placed in direct contact with the non-device side of a die. In these instances the electroosmotic pump may be part of a microelectronic package containing the die or the thermal management chip.
    Type: Application
    Filed: November 24, 2003
    Publication date: May 26, 2005
    Inventors: Alan Myers, Sarah Kim, R. List
  • Publication number: 20050095751
    Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.
    Type: Application
    Filed: November 8, 2004
    Publication date: May 5, 2005
    Inventors: Stefan Hau-Riege, R. List