Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
The present patent application is a Continuation Application of, and claims priority to, Ser. No. 10/855,032, filed on May 26, 2004, which is a Divisional Application of, and claims priority to, Ser. No. 10/077,967, filed Feb. 20, 2002, which issued as U.S. Pat. No. 6,762,076 on Jul. 13, 2004.
This application is related to the following patents and pending applications, which are assigned to the assignee of this application: U.S. Pat. No. 6,661,085, filed on Feb. 6, 2002 and issued on Dec. 9, 2003; U.S. patent application Ser. No. 10/066,643, filed on Feb. 6, 2002 and issued as U.S. Pat. No. 6,975,016 on Dec. 13, 2005; U.S. patent application Ser. No. 10/066,645, filed on Feb. 6, 2002 and issued as U.S. Pat. No. 6,887,769 on May 3, 2005; U.S. patent application Ser. No. 10/613,006, filed on Jul. 7, 2003 and which has been allowed; and U.S. patent application Ser. No. 10/695,328, filed on Oct. 27, 2003 and issued as U.S. Pat. No. 7,037,804 on May 2, 2006.
TECHNICAL-FIELDThe present invention relates to a semiconductor process and, more specifically, relates to a process of vertically stacking multiple wafers supporting different active IC devices on a single die with low cost and high via density with optimum metal bonding areas.
BACKGROUNDIntegrated circuits (ICs) form the basis for many electronic systems. Essentially, an integrated circuit (IC) includes a vast number of transistors and other circuit elements that are formed on a single semiconductor wafer or chip and are interconnected to implement a desired function. The complexity of these integrated circuits (ICs) requires the use of an ever increasing number of linked transistors and other circuit elements.
Many modern electronic systems are created through the use of a variety of different integrated circuits; each integrated circuit (IC) performing one or more specific functions. For example, computer systems include at least one microprocessor and a number of memory chips. Conventionally, each of these integrated circuits (ICs) is formed on a separate chip, packaged independently and interconnected on, for example, a printed circuit board (PCB).
As integrated circuit (IC) technology progresses, there is a growing desire for a “system on a chip” in which the functionality of all of the IC devices of the system are packaged together without a conventional PCB. Ideally, a computing system should be fabricated with all the necessary IC devices on a single chip. In practice, however, it is very difficult to implement a truly high-performance “system on a chip” because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits.
As a compromise, various “system modules” have been introduced that electrically connect and package integrated circuit (IC) devices which are fabricated on the same or on different semiconductor wafers. Initially, system modules have been created by simply stacking two chips, e.g., a logic and memory chip, one on top of the other in an arrangement commonly referred to as chip-on-chip structure. Subsequently, multi-chip module (MCM) technology has been utilized to stack a number of chips on a common substrate to reduce the overall size and weight of the package, which directly translates into reduced system size.
Existing multi-chip module (MCM) technology is known to provide performance enhancements over single chip or chip-on-chip (COC) packaging approaches. For example, when several semiconductor chips are mounted and interconnected on a common substrate through very high density interconnects, higher silicon packaging density and shorter chip-to-chip interconnections can be achieved. In addition, low dielectric constant materials and higher wiring density can also be obtained which lead to the increased system speed and reliability, and the reduced weight, volume, power consumption and heat to be dissipated for the same level of performance. However, MCM approaches still suffer from additional problems, such as bulky package, wire length and wire bonding that gives rise to stray inductances that interfere with the operation of the system module.
An advanced three-dimensional (3D) wafer-to-wafer vertical stack technology has been recently proposed by researchers to realize the ideal high-performance “system on a chip” as described in “Face To Face Wafer Bonding For 3D Chip Stack Fabrication To Shorten Wire Lengths” by J. F. McDonald et al., Rensselaer Polytechnic Institute (RPI) presented on Jun. 27-29, 2000 VMIC Conference, and “Copper Wafer Bonding” by A. Fan et al., Massachusetts Institute of Technology (MIT), Electrochemical and Solid-State Letters, 2 (10) 534-536 (1999). In contrast to the existing multi-chip module (MCM) technology which seeks to stack multiple chips on a common substrate, 3-D wafer-to-wafer vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices inside a single chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance.
One major challenge of 3-D wafer-to-wafer vertical stack integration technology is the bonding between wafers and between die in a single chip. In the RPI publication, polymer glue is used to bond the vertically stacked wafers. In the MIT publication, copper (Cu) is used to bond the vertically stacked wafers; however, a handle (carrier wafer) is required to transport thinly stacked wafers and a polymer glue is also used to affix the handle on the top wafer during the vertically stacked wafer processing. As a result, there is a need for a simpler but more efficient process of vertically stacking multiple wafers supporting different active IC devices on a single die with low cost and high via density with optimum metal bonding areas.
BRIEF DESCRIPTION OF THE DRAWINGSA more complete appreciation of exemplary embodiments of the present invention, and many of the attendant advantages of the present invention, will become readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
The present invention is applicable for use with all types of semiconductor wafers and integrated circuit (IC) devices, including, for example, MOS transistors, CMOS devices, MOSFETs, and new memory devices and communication devices such as smart cards, cellular phones, electronic tags, and gaming devices which may become available as semiconductor technology develops in the future. However, for the sake of simplicity, discussions will concentrate mainly on exemplary use a three-dimensional (3-D) wafer-to-wafer vertical stack, although the scope of the present invention is not limited thereto.
Attention now is directed to the drawings and particularly to
According to one aspect of the present invention, however, a metal to metal bond can be used to stack wafers 110, 120 and 130 to form the vertical stack 100. This metal to metal bond method may serve not only as electrical connections to active IC devices on the vertically stacked wafers 110, 120 and 130 on a 3-D wafer-to-wafer vertical stack 100 but also bond adjacent wafers 110, 120 and 130. Dummy metal, bonding pads can also be made to increase the surface area for wafer to wafer bonding and serve as auxiliary structures such as ground planes or heat conduits for the active IC devices. In addition, improved etch stop layers for the Si via etch can be used in vertically stacked wafer processing (i.e., 3-D interconnect processing) which provide more efficient electrical conductivity between vertically stacked wafers 110, 120 and 130.
Turning now to
As shown in
In the example 2-wafer vertical stack 200 shown in
After the wafer bonding process is completed, the top wafer 220 can also be thinned for a subsequent silicon (Si) via process. Thereafter, one or more interwafer (interconnect) vias (or via holes) 226 can be etched, via the top wafer 220, to establish electrical connections between active IC devices on the vertically stacked wafers 210 and 220 and an external interconnect (not shown), via a C4 bump 228. Interwafer vias 226 can be formed employing damascene technology, that is, forming an opening, e.g., a damascene opening in the ILD layer 224 through the active layer 222, depositing a diffusion barrier layer, typically tantalum (Ta), titanium (Ti), or tungsten (W), and filling the opening with copper (Cu) or a Cu alloy. The opening in the ILD layer 224 can be filled by initially depositing a seed layer and then electroplating the copper (Cu) or Cu alloy layer. The seed layer typically comprises copper (Cu), though other materials such as refractory metals have been suggested. Both the seed layer and barrier layer are typically deposited by a Physical Vapor Deposition (PVD) process and, for purposes of simplification, can be referred to as a single barrier/seed layer. Chemical Mechanical Polish (CMP) can then be performed such that the upper surface of the Cu or Cu alloy layer is substantially coplanar with the upper surface of the active Si layer 222.
As shown in
As shown in
In another example technique, the silicon (Si) layer 222 and the oxide layer 224 of the top wafer 220 can be etched in the same step. A thin layer of oxide 320 can then be deposited on the interwafer vias 226 so as to protect and insulate the sidewall of the interwafer vias 226. Then anisotropic oxide etch can be performed to remove the thin layer of oxide 320 at the bottom of the interwafer vias 226. In other words, the silicon (Si) via etch and the oxide via etch are performed at the same time. Oxide is then deposited in the interwafer vias 226 and anisotropic oxide via etch is performed to clear a thin layer of oxide at the bottom of the interwafer vias 226.
After the oxide etch or the anisotropic oxide etch, a barrier/seed layer 330 can then deposited inside the oxide via. Such a barrier/seed layer 330 contains a barrier layer deposited on the oxide layer 320 and a seed layer deposited on the barrier layer using, for example, a Chemical Vapor Deposition (CVD) process. The barrier layer can be a single or a stack of materials selected from the groups of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W). The seed layer can be a few layers of copper (Cu) atoms deposited on the barrier layer by a Chemical Vapor Deposition (CVD) process.
After the barrier/seed layer 330, copper (Cu) 340 can then be deposited in the interwafer vias 226, via electroplating and Chemical Mechanical Polish (CMP), to establish electrical connections of active IC devices between vertically stacked wafers 210 and 220 to an external interconnect, via the C4 bump 228 shown in
However, in the example 2-wafer vertical stack 400 shown in
As shown in
After the anisotropic oxide etch, a barrier/seed layer 530 can then deposited on the oxide layer 520 and the bottom of the interwafer vias 426. After the barrier/seed layer 530, copper (Cu) 540 can then be deposited in the interwafer vias 426, via electroplating and Chemical Mechanical Polish (CMP), to establish electrical connections between active IC devices on the vertically stacked wafers 410 and 420 and an external interconnect (not shown), via the C4 bump 428 shown in
In both the example 2-wafer vertical stack 200 shown in
For example,
In the example 3-D wafer-to-wafer vertical stacks as described with reference to
According to another aspect of the present invention, effective metal bonding areas on opposing surfaces of vertically stacked wafers can be made increased without consuming active silicon (Si) area by using one or more dummy Si vias, tapered Si vias, or incorporating an existing copper (Cu) dual damascene process.
For example,
After the first two wafers are bonded in the same manner as described with reference to
The barrier/seed layer 754 can comprise a barrier layer deposited overlying the active layer 722 and the ILD 724 and a copper (Cu) seed layer deposited overlying the barrier layer. The barrier layer is typically comprised of a material that can eliminate out-diffusion of copper (Cu) ions from the dual damascene interconnect into the ILD layer 724, and serve as a catalyst for the copper (Cu) deposition reaction. The barrier layer preferably comprises one of the group containing: tantalum, titanium, and tungsten. The copper (Cu) seed layer deposited on the barrier layer can be made very thin while still exhibiting excellent step coverage or conformity. The copper (Cu) dual damascene process advantageously increases (Cu) metal bonding areas for multiple wafer to-wafer bonding in an example 3-D wafer-to-wafer vertical stack 700 shown in
After the first two wafers are bonded in the same manner as described with reference to
For example, the active Si layer 824 of wafer #2 820 can be etched to form Si vias 850 and dummy vias 860. An oxide layer (not shown) can then be deposited only on the Si vias 850 so as to protect and insulate the sidewall of the Si vias 850. The oxide layer (not shown) deposited on the Si vias 850 can again be patterned and etched to form a lower contact or via hole (trench) section in the ILD layer 824 with the lower level metalization, e.g., metallic line (metal bonding layer 106). A barrier/seed layer (not shown) can then be deposited overlying the active layer 822 and the ILD 824 in the vias and trenches. Copper (Cu) is then deposited by electroplating or any other Cu deposition techniques such as metal-organic chemical vapor deposition (CVD) or plasma-enhanced metal-organic CVD. As a result, dummy vias 860 can serve as additional metal bonding pads to increase the surface of (Cu) metal bonding areas for multiple (>2) wafer to-wafer bonding in an example 3-D wafer-to-wafer vertical stack 800, as shown in
After the first two wafers are bonded in the same manner as described with reference to
The example Si via process can be described as follows: The active Si layer 924 of wafer #2 920 can first be patterned and etched at a predetermined angle to form tapered vias 950. An oxide layer (not shown) can then be deposited only on the tapered vias 950 so as to protect and insulate the sidewall of the tapered vias 950. The oxide layer (not shown) deposited on the tapered vias 950 can again be patterned and etched to form a lower contact or via hole section in the ILD layer 924 with the lower level metalization, e.g., metallic line (metal bonding layer 106). A barrier/seed layer (not shown) can then be deposited overlying the active layer 922 and the ILD 924 in the tapered vias 950. Copper (Cu) is then deposited by electroplating or any other Cu deposition techniques such as metal-organic chemical vapor deposition (CVD) or plasma-enhanced metal-organic CVD.
As described in this invention, there are several processes of vertically stacking multiple wafers supporting different active IC devices with low cost and high via density. Metal bonding areas on wafers can be increased by using either a copper (Cu) dual damascene process, dummy vias, or tapered vias to effectively bond vertically stacked wafers and establish electrical connections between active IC devices on the vertically stacked wafers and an external interconnect (not shown), via C4 bumps.
While there have been illustrated and described what are considered to be exemplary embodiments of the present invention, it will be understood by those skilled in the art and as technology develops that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the present invention. Many modifications may be made to adapt the teachings of the present invention to a particular situation without departing from the scope thereof. Therefore, it is intended that the present invention not be limited to the various exemplary embodiments disclosed, but that the present invention includes all embodiments falling within the scope of the appended claims.
Claims
1. A method of metal bonding vertically stacked wafer pairs comprising:
- forming a first wafer pair, including bonding a metallic line disposed on an ILD on a front side of a first wafer to a corresponding metallic line disposed on an ILD on a front side of a second wafer;
- forming a second wafer pair, including bonding a metallic line disposed on an ILD on a front side of a third wafer to a corresponding metallic line disposed on an ILD on a front side of a fourth wafer;
- providing a first metal bonding area at a back side of the second wafer and a second metal bonding area at a back side of the third wafer, said providing including forming an Si via through an active layer at a back side of the second wafer, wherein a first end of the Si via connects to the metallic line of the second wafer and a second end of the Si via is exposed at the back side of the second wafer;
- increasing the first and second metal bonding areas; and
- bonding the increased first metal bonding area to the increased second metal bonding area.
2. The method of claim 1, wherein increasing the metal bonding areas comprises:
- increasing a horizontal cross-sectional area of the second end of the Si via.
3. The method of claim 2, wherein increasing the horizontal cross-sectional area comprises:
- forming an upper trench section in the back side of the second wafer, the upper trench section filled with a conductive material and connected to the Si via.
4. The method of claim 2, wherein increasing the horizontal cross-sectional area comprises:
- etching the first Si via to form a tapered via.
5. The method of claim 1, wherein increasing the metal bonding areas comprises:
- forming a dummy Si via in the active layer of the second wafer and a corresponding dummy Si via in the active layer of the third wafer.
6. The method of claim 5, wherein forming each dummy Si via comprises forming each dummy Si via to have a diameter smaller than a diameter of the first Si via.
7. The method of claim 1, further comprising:
- thinning the back side of the second wafer.
8. The method of claim 1, further comprising:
- forming a microprocessor in the first wafer;
- forming a memory device in the second wafer; and
- forming a communication device in the third or fourth wafer.
9. A method of metal bonding multiple vertically stacked wafers comprising:
- depositing a first metallic line on an ILD of a front side of a first wafer;
- depositing a second metallic line on an ILD of a front side of a second wafer;
- bonding the first metallic line to the second metallic line;
- depositing a third metallic line on an ILD of a front side of a third wafer;
- depositing a fourth metallic line on an ILD of a front side of a fourth wafer;
- bonding the third metallic line to the fourth metallic line;
- forming a first Si via through an active layer at a back side of the second wafer, the first Si via having an internal end connected to the second metallic line and an external end exposed at the back side of the second wafer;
- forming a second Si via through an active layer at a back side of the third wafer, the second Si via having an internal end connected to the third metallic line and an external end exposed at the back side of the third wafer;
- increasing areas of the external ends of the first and second Si vias; and
- bonding the areas.
10. The method of claim 9, wherein increasing the areas comprises:
- forming a trench section in the back side of the second wafer, the trench section filled with a conductive material and connected to the first Si via; and
- forming a corresponding trench section in the back side of the third wafer, the corresponding trench section filled with the conductive material and connected to the second Si via.
11. The method of claim 9, wherein increasing the areas comprises:
- etching the active layer at the back side of the second wafer at an angle, such that the first Si via is tapered and has a larger cross-sectional area at the external end than at the corresponding internal end.
12. The method of claim 11, further comprising:
- forming a third Si via through an active layer at a back side of the fourth wafer, the third Si via connecting to the fourth metallic line of the fourth wafer.
13. The method of claim 12, wherein forming the third Si via comprises:
- etching the active layer at the back side of the fourth wafer to form a hole;
- depositing oxide on surfaces of the hole;
- removing oxide at a bottom surface of the hole using an anisotropic oxide etch;
- depositing a barrier layer on oxide on sidewalls of the hole;
- depositing a seed layer on the barrier layer; and
- filling the hole with a conductive material.
14. The method of claim 13, wherein the barrier layer is composed of a material selected from the group consisting of: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W).
15. The method of claim 13, wherein the seed layer comprises a layer of copper atoms deposited by CVD.
16. The method of claim 12, further comprising:
- forming a C4 bump on the fourth wafer, the C4 bump physically connecting to the third Si via and electrically connecting to an active layer at a back side of the first wafer.
17. A method of metal bonding back sides of two wafers comprising:
- forming a first Si via through an active layer at a back side of a first wafer, wherein a first end of the first Si via is exposed;
- forming a second Si via through an active layer at a back side of a second wafer, wherein a second end of the second Si via is exposed;
- increasing areas of the first end and second end; and
- bonding the increased areas.
18. The method of claim 12, wherein forming the first Si via comprises:
- etching a part of the active layer at the back side of the first wafer, said etching stopping a tungsten etch stop disposed at an interface between the active layer at the back side of the first wafer and an ILD layer at a front side of the first wafer.
19. The method of claim 17, wherein increasing the areas comprises:
- forming a first trench section in the back side of the first wafer, the first trench section filled with a conductive material and connected to the first Si via; and
- forming a second trench section in the back side of the second wafer, the second trench section filled with the conductive material and connected to the second Si via.
20. The method of claim 17, further comprising:
- forming a first dummy via in the active layer of the first wafer;
- forming a second dummy via in the active layer of the second wafer; and
- bonding the first and second dummy vias.
Type: Application
Filed: Nov 21, 2006
Publication Date: May 17, 2007
Inventors: Sarah Kim (Portland, OR), R. List (Beaverton, OR), Scot Kellar (Bend, OR)
Application Number: 11/603,521
International Classification: H01L 21/00 (20060101);