Abstract: An isolated gate driver includes a first input terminal to receive gate information and one or more input terminals to receive configuration information. A modulation circuit generates a modulated signal having four possible states, each of the four possible states corresponding to a different unique pair of values of the gate information and the configuration information. The modulation circuit represents two of the states using on-off keying (OOK) while the configuration information is at a first value and represents two of the states as a modification to the OOK modulation based on the configuration information being at a second value. The modulated signal is sent over an isolation communication channel coupling a transmitter and receiver of the isolated gate driver.

Abstract: Embodiments provide for methods, computer program products, and systems to improve media playback comprising receiving a variant stream, identifying respective maximum segment durations for a plurality of different types of client devices that will play media content contained in the variant stream, generating, using the variant stream, a respective playlist for each of the plurality of different types of client devices, wherein the respective playlists each contain different maximum segment durations, and delivering the respective playlists to at least one of the plurality of different types of client devices via a distribution network.

Abstract: An isolated gate driver includes a first input terminal to receive gate information and one or more input terminals to receive configuration information. A modulation circuit generates a modulated signal having four possible states, each of the four possible states corresponding to a different unique pair of values of the gate information and the configuration information. The modulation circuit represents two of the states using on-off keying (OOK) while the configuration information is at a first value and represents two of the states as a modification to the OOK modulation based on the configuration information being at a second value. The modulated signal is sent over an isolation communication channel coupling a transmitter and receiver of the isolated gate driver.

Abstract: A system comprises a GNSS receiver that receives a GNSS signal and produces GNSS measurements; a plurality of inertial sensors that produce inertial data; and a navigation system comprising a Kalman filter and an inertial navigation unit. The Kalman filter receives the GNSS measurements and calculates pseudo-range residuals, delta-range residuals, pseudo-range chi square values, delta-range chi square values, accelerometer bias estimates, and gyroscope bias estimates. A spoof detection system communicates with the Kalman filter and comprises a set of detection monitors that determine an integrity of the GNSS measurements. The detection monitors detect if the pseudo-range residuals, the delta-range residuals, the pseudo-range chi-square values, the delta-range chi-square values, the accelerometer bias estimates, or the gyroscope bias estimates, go beyond a fail threshold indicating that the GNSS signal is abnormal.

Abstract: A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit.

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.

Abstract: A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit.

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

Abstract: An isolated gate driver includes a first input terminal to receive gate information and one or more input terminals to receive configuration information. A modulation circuit generates a modulated signal having four possible states, each of the four possible states corresponding to a different unique pair of values of the gate information and the configuration information. The modulation circuit represents two of the states using on-off keying (OOK) while the configuration information is at a first value and represents two of the states as a modification to the OOK modulation based on the configuration information being at a second value. The modulated signal is sent over an isolation communication channel coupling a transmitter and receiver of the isolated gate driver.

Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

Abstract: Provided herein is a method for identifying a mastitis-causing microbe in a subject. A milk sample is centrifuged to form a microbial pellet, total nucleic acids are extracted from the pellet and a microarray analysis of extracted DNA from which the mastitis-causing microbe is identified from DNA hybridization to mastitis-causing microbe species-specific gene probes. Also provided is a method for diagnosing a bovine mastitis infection in a dairy cow after identifying the bovine mastitis-causing microbe in a raw milk sample from the dairy cow.

Abstract: A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.

Abstract: A first die is communicatively coupled to a first isolation communication channel and a second isolation communication channel and configured to send a first heartbeat signal over the first isolation communication channel. A second die is coupled to receive the first heartbeat signal from the first die over the first isolation communication channel and to supply a second heartbeat signal to the second isolation communication channel. The first die enters a first die low power mode responsive to detecting an absence of the second heartbeat signal and the second die enters a second die low power mode responsive to detecting an absence of the first heartbeat signal. The first and second die use low power oscillators in the low power mode to supply the heartbeat signals.

Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.

Abstract: A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.

Abstract: Provided are methods for amplifying a gene or RNA or sets thereof of interest using a tandem PCR process. The primers in the first PCR or set of PCR reactions are locus-specific. The primers in the second PCR or set of PCR reactions are specific for a sub-sequence of the locus-specific primers and completely consumed during the second PCR amplification. For RNA amplification, the first PCR is reverse transcription and the resulting cDNA(s) provide a template for cRNA synthesis, endpoint PCR or real time PCR. Also provided is a tandem PCR method which accepts raw, completely unpurified mouthwash, cheek swabs and ORAGENE-stabilized saliva as the sample input, the resulting amplicons serving as the substrate for complex, microarray-based genetic testing. Also provided is a method of allelotyping a gene or set thereof by amplifying the gene(s) using tandem PCR on DNA or RNA comprising the sample.