Abstract: A data caching method comprising monitoring read and write requests submitted for accessing target data in a first data block on a storage medium; identifying a sequence of access requests for target data as a first stream; and determining whether the first stream is suitable for direct disk access based on inter-arrival times of the read or write requests in the stream.

Abstract: Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline an isochronous request, and communicating the isochronous request and completion deadline information to the data storage device. Apparatus embodiments generally comprise a request identifier to identify an isochronous request, a logic module to assign a completion deadline to the isochronous request, and a communication module to communicate the isochronous request and the completion deadline to a data storage device. Alternative apparatus embodiments may include a monitor module to monitor a system process operating in the system and determine if the system process issues isochronous requests.

Abstract: Disclosed is a method for handling conflicting deadlines by a disk drive. The method comprises: receiving a plurality of requests from a plurality of applications for accessing the disk drive; determining a plurality of service times for the plurality of requests; serving a first request of the plurality of request prior to an actual schedule when a deadline for serving the first request and a deadline for serving a subsequent request of the plurality of requests cannot be simultaneously met by the disk drive; and serving the subsequent request after the first request is served by the disk drive.

Abstract: A method for synchronizing testing of shared memory contained in a multi-processor computer system after reset. The method involves the steps of performing a wake-up procedure by a bootstrap processor on the other processors. Thus, the other processors can assist in testing the shared memory. Next, respective portions of the shared memory are allocated to each of the processors. Finally, upon completion of testing of its respective portion of the shared memory, each processor sets its unique storage unit synchronizing the processors at completion.

Abstract: A power down control mechanism for multiprocessor computer systems. A power down register is maintained for providing a power down control signal to the multiple processing units in the multiprocessing system. Individual processing units can be selectively onlined or offlined as needed. In addition, during system initialization, the power down mechanism of the present invention can be used for onlining additional processors and also used for preventing faulty processors from attempting to become the system's boot system processor.

Abstract: In a shared memory computer system, processing nodes are coupled together by way of cluster bridges. A cluster bridge operating according to the present invention intercepts a global access transaction request issued from a processing node and issues a transaction deferral to indicate that the request will be serviced out-of-order. A map of global addresses which correspond to fixed addresses at the node from which the access request was issued is maintained by the cluster bridge. If the address of the global access transaction request corresponds to a fixed address local to the requesting node, the address is translated at cluster bridge and accessed at the local node in order to complete the deferred request.

Abstract: An arbiter for the local bus of a computer system. The system contains a bridge and a plurality of agent devices that are all connected to a local bus. The bridge links the local system to a remote system. The bridge and one of the agents (DEFER agent) within the local system can communicate in correspondence with the Non-uniform memory access(NUMA) standard. The local system also contains an agent (DEFERless agent) that does not comply with the NUMA standard. The arbiter provides access to the local bus in response to a request from one of the agents on a corresponding bus access signal line. If the DEFERless agent generates a remote access request and the bridge cannot immediately service the request, the bridge provides a negative acknowledge to the agent and disables the DEFERless agent bus access signal so that the DEFERless agent cannot control the local bus. The remaining agents can access the local bus even when the DEFERless agent is waiting for service from the bridge.