Abstract: Disclosed are methods of a method of making a nanostructure, comprising adding a component A (compA) protein to a solution comprising a component B (compB) protein under conditions that minimize shear stress, thereby forming a compA:compB complex. Further disclosed are methods of making a nanostructure, comprising (i) providing a first inlet fluid stream comprising a first protein and a second inlet fluid stream comprising a second protein, and (ii) contacting the first inlet fluid stream and the second inlet fluid stream to form an outlet stream, wherein mixing of the first protein and the second protein occurs in the outlet stream, thereby forming a protein complex comprises the first protein and the second protein. A microfluidic mixer may be used. The methods may further comprise purifying the compA:compB complex from excess compA, excess compB, and/or other impurities by filtering the solution with a 1,000 kDa membrane or an equivalent thereof.

Abstract: The present invention relates to a method of treating fatty liver disease in a subject in need thereof comprising administering to the subject a therapeutically effective amount of a compound of Formula (I) 5?-N1N2N3N4N5N6-N7N8-dCm-dGc-N11N12N13N14N15N16-N17N18-3?. The fatty liver disease can be non-alcoholic fatty liver disease, such as simple fatty liver disease or NASH. The invention also relates to the use of adiponectin as a biomarker for identifying subjects more likely to respond to treatment with the compound on Formula (I) 5?-N1N2N3N4N5N6-N7N8-dCm-dGc-N11N12N13N14N15N16-N17N18-3? and for assessing response of the subject during treatment with the compound of Formula (I) 5?-N1N2N3N4N5N6-N7N8-dCm-dGc-N11N12N13N14N15N16-N17N18-3?.

Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

Abstract: Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a SHE-MRAM device. The SHE-MRAM device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. The second leads are made of a material having large spin orbit interactions and high electrical resistivity. The SHE-MRAM device further includes a periphery circuitry having multiple pairs of transistors. The multiple pairs of transistors reduce the length a current has to flow through a second lead of the plurality of second leads. By limiting the distance a current can flow through the second lead, applying excessive voltage to the second lead is avoided.

Abstract: A wireless communication system for use in a process environment uses mesh and possibly a combination of mesh and point-to-point communications to produce a wireless communication network that can be easily set up, configured, changed and monitored, thereby making a wireless communication network that is less expensive, and more robust and reliable. The wireless communication system allows virtual communication paths to be established and used within the process control system in a manner that is independent of the manner in which the wireless signals are sent between different wireless transmitting and receiving devices within the process plant. Still further, communication analysis tools are provided to enable a user or operator to view the operation of the wireless communication network to thereby analyze the ongoing operation of the wireless communications within the wireless communication network.

Abstract: A process control system coordinates with an associated asset management system to implement a plant safety mechanism and, in particular, to prevent unintended changes to, or otherwise undesired operation of, one or more process control equipment resources in a process plant. A maintenance technician uses the asset management system to request access to one or more of the process control equipment resources. A process operator receives the request via the process control system and grants or denies the request. Process control equipment resources for which a process operator grants a request are inoperable, in part or in whole, by the process control system. Upon completion of the maintenance task, the maintenance technician requests to return control of the process control equipment resource to the process operator. The return is complete when the process operator acknowledges the return of the resource to the process control system.

Abstract: A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.

Abstract: A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.

Abstract: A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Mem resistors).

Abstract: The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors).

Abstract: The present invention relates to peptide nucleic acid (PNA) probes, PNA probe sets and methods for the analysis of Gram positive and Gram negative organisms optionally present in a sample. The invention further relates to diagnostic kits comprising such PNA probes.

Abstract: Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a SHE-MRAM device. The SHE-MRAM device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. The second leads are made of a material having large spin orbit interactions and high electrical resistivity. The SHE-MRAM device further includes a periphery circuitry having multiple pairs of transistors. The multiple pairs of transistors reduce the length a current has to flow through a second lead of the plurality of second leads. By limiting the distance a current can flow through the second lead, applying excessive voltage to the second lead is avoided.

Abstract: Embodiments of the present disclosure generally relate to memory devices having nano-imprinted patterns interconnected to conventionally processed circuitry and a method of fabrication thereof. The memory device includes a plurality of conductive traces, a substrate having a plurality of conductive pads and a plurality of conductive posts. Each conductive pad is sized to account for alignment error inherent in the nano-imprinting process. Each conductive post is coupled between a conductive trace and a conductive pad allowing interconnection of the very finely sized features of nano-imprint lithography to the larger features of a conventionally patterned wafer.

Abstract: A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.

Abstract: In various embodiments, a memory storage element for storing two or more bits of information is formed by connecting two resistive change elements in series whereby the first resistive change element is made of a first material and the second resistive change element is made of a second material and the melting point of the first resistive change element material is greater than the melting point of the second resistive change element material such that the set and reset states of the two elements can be written and read.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: In various embodiments, a memory cell for storing two or more bits of information includes two series-connected memory storage elements composed of programmable materials having different melting points, enabling independent programming of the storage elements via different current pulses.

Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.