Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: The present invention is a method for forming a vertically oriented element having a narrower area near its center away from either end. The present invention will find applicability in other memory cell structures. The element will have a narrow portion towards its center such that current density will be higher away from the ends of the element. In this way, the heating will occur away from the ends of the storage element. Heating in a phase-change or resistive change element leads to end of life conditions, including the condition whereby contaminants from the end point contacts are enabled to migrate away from the end point and into the storage element thereby contaminating the storage element material and reducing its ability to be programmed, erased and/or read back.

Abstract: A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6 F2.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: Methods of forming memory devices include providing a substrate, forming source, channel, and drain layers over the substrate, and patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F2. The channel layer has a doping type different from a doping type of the source layer, and the drain layer has a doping type different from a doping type of the channel layer.

Abstract: A vertically oriented memory element having a narrower area near its center away from its ends is formed. Current density and heating are higher away from the ends of the memory element, thus increasing its lifetime.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

Abstract: The present invention relates to peptide nucleic acid (PNA) probes, PNA probe sets and methods for the analysis of Gram positive and Gram negative organisms optionally present in a sample. The invention further relates to diagnostic kits comprising such PNA probes.

Abstract: RNA interference is provided for inhibition of connective tissue growth factor mRNA expression in ocular disorders involving CTGF expression. Ocular disorders involving aberrant CTGF expression include glaucoma, macular degeneration, diabetic retinopathy, choroidal neovascularization, proliferative vitreoretinopathy and wound healing. Such disorders are treated by administering interfering RNAs of the present invention.

Abstract: A method and system of communicating between a wireless network and a process control system communicatively coupled to a server, such as OPC. The server receives data from the wireless network, where the data is generated from an input/output data point within the wireless network. The server maps the data between the input/output data point and a data point placeholder within the process control system. The server writes the mapped data to the corresponding data point placeholder of the process control system via a process control interface, and the mapped data is provided to the process control system as process control data native to the process control system. Process control data may also be provided to the server, mapped between a data point placeholder of the process control system and an input/output data point of the wireless network, and written to the corresponding input/output data point.

Abstract: An application programming interface schema, method and system for communicating between first and second application programming interfaces within a process control system includes processing a call from a first application programming interface for a data request, translating the data request from the first application programming interface into one or more methods of a unified application programming interface, and implementing the one or more methods of the unified application programming interface with a second application programming interface. A first unified layer receives a transmission request from a proprietary application programming interface, and translates the transmission request into one or more methods of a unified application programming interface. A second unified layer implements methods of the unified application programming interface with the wireless network application programming interface.

Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.

Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Abstract: In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets of conductors and a selectable resistance element. All storage element address paths have substantially equivalent voltage drops across the corresponding storage elements.

Abstract: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.

Abstract: A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

Abstract: A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection.

Abstract: A process control system coordinates with an associated asset management system to implement a plant safety mechanism and, in particular, to prevent unintended changes to, or otherwise undesired operation of, one or more process control equipment resources in a process plant. A maintenance technician uses the asset management system to request access to one or more of the process control equipment resources. A process operator receives the request via the process control system and grants or denies the request. Process control equipment resources for which a process operator grants a request are inoperable, in part or in whole, by the process control system. Upon completion of the maintenance task, the maintenance technician requests to return control of the process control equipment resource to the process operator. The return is complete when the process operator acknowledges the return of the resource to the process control system.