Abstract: An apparatus for surface enhanced Raman spectroscopy includes a substrate, a nanostructure and a plasmonic material. The nanostructure and the plasmonic material are integrated together to provide electronic and plasmonic enhancement to a Raman signal produced by electromagnetic radiation scattering from an analyte.

Abstract: A sensor for surface enhanced Raman spectroscopy (SERS) sensor includes surfaces and an actuator to adjust an intersurface spacing between the surfaces to contain an analyte and allow the analyte to be released from containment.

Abstract: A memristor array includes a lower layer of crossbars, upper layer of crossbars intersecting the lower layer of crossbars, memristor cells interposed between intersecting crossbars, and pores separating adjacent memristor cells. A method forming a memristor array is also provided.

Abstract: Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.

Abstract: Examples of integrated sensors are disclosed herein. An example of an integrated sensor includes a flexible substrate, and an array of spaced apart sensing members formed on a surface of the flexible substrate. Each of the spaced apart sensing members includes a plurality of polygon assemblies. The polygon assemblies are arranged in a controlled pattern on the surface of the flexible substrate such that each of the plurality of polygon assemblies is a predetermined distance from each other of the plurality of polygon assemblies, and each of the plurality of polygon assemblies including collapsible signal amplifying structures controllably positioned in a predetermined geometric shape.

Abstract: Memristive elements are provided that include an active region disposed between a first electrode and a second electrode, the active region including two switching layers formed of a switching material capable of carrying a species of dopants and a conductive layer formed of a dopant source material. Memristive elements also are provided that include two active regions disposed between a first electrode and a second electrode, and a third electrode being disposed between and in electrical contact with both of the active regions. Each of the active regions include a switching layer formed of a switching material capable of carrying a species of dopants and a conductive layer formed of a dopant source material. Multilayer structures including the memristive elements also are provided.

Abstract: A stateful negative differential resistance device includes a first conductive electrode and a second conductive electrode. The device also includes a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy and a second material comprising a differential resistance that is negative in a locally active region. The first material and second material are sandwiched between the first conductive electrode and second conductive electrode. A method for using a stateful NDR device includes applying programming energy to the stateful NDR device to set a state of the stateful NDR device to a predetermined state and removing electrical power from the stateful NDR device. Power-up energy is applied to the stateful NDR device such that the stateful NDR device returns to the predetermined state.

Abstract: A capacitive crossbar array includes a first set of conductors and a second set of conductors which intersect to form crosspoints. A nonlinear capacitive device is interposed between a first conductor within the first set and a second conductor within the second set at a crosspoint. The nonlinear capacitive device is configured to store information which is accessible through said first conductor and said second conductor. A method for utilizing a capacitive crossbar array is also provided.

Abstract: A memristive device is disclosed herein. The device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two mobile species are present in the active region. Each of the at least two mobile species is configured to define a separate state variable of the memristive device.

Abstract: Apparatus and methods related to negative differential resistance (NDR) are provided. An NDR device includes a spaced pair of electrodes and at least two different materials disposed there between. One of the two materials is characterized by negative thermal expansion, while the other material is characterized by positive thermal expansion. The two materials are further characterized by distinct electrical resistivities. The NDR device is characterized by a non-linear electrical resistance curve that includes a negative differential resistance range. The NDR device operates along the curve in accordance with an applied voltage across the pair of electrodes.

Abstract: Apparatus, methods, and hollow metal waveguides to perform surface-enhanced Raman spectroscopy are disclosed. An example apparatus includes a hollow metal waveguide to direct Raman photons from an intermediate location within a volume of the hollow metal waveguide toward a distal end of the hollow metal waveguide, and a mirror to direct incident light from a light source to the intermediate location within the volume of the hollow metal waveguide and to direct at least some of the Raman photons toward the distal end.

Abstract: A memristive device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle. An active region is disposed between the first and second electrodes. The active region has defects therein. Graphene or graphite is disposed between the active region and the first electrode and/or between the active region and the second electrode.

Abstract: A memristive routing device includes a memristive matrix, mobile dopants moving with the memristive matrix in response to programming electrical fields and remaining stable within the memristive matrix in the absence of the programming electrical fields; and at least three electrodes surrounding the memristive matrix. A method for tuning electrical circuits with a memristive device includes measuring a circuit characteristic and applying a programming voltage to the memristive device which causes motion of dopants within the memristive device to alter the circuit characteristic. A method for increasing a switching speed of a memristive device includes drawing dopants from two geometrically separated locations into close proximity to form two conductive regions and then switching the memristive device to a conductive state by applying a programming voltage which rapidly merges the two conductive regions to form a conductive pathway between a source electrode and a drain electrode.

Abstract: An optoelectronic memory cell has a transparent top electrode, a photoactive layer, a latching layer, and a bottom electrode. The photoactive layer absorbs photons transmitted through the top electrode and generates charge carriers. During light exposure, the latching layer changes its resistance under an applied electric field in response to the generation of charge carriers in the photoactive layer.

Abstract: A display matrix may have a resistance switch and a display element formed on a common display substrate. The resistance switch may have a metal insulator transition (MIT) material that has a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance.

Abstract: Chaotic oscillator-based random number generation is described. In an example, a circuit includes a negative differential resistance (NDR) device to receive an alternating current (AC) bias. The circuit further includes a capacitance in parallel with the NDR device, the capacitance having a value such that, in response to a direct current (DC) bias applied to the NDR device and the capacitance, a voltage across the capacitance oscillates with a chaotic period. The circuit further includes a random number generator to generate random numbers using samples of the voltage across the capacitance.

Abstract: A memelectronic device may have a first and a second electrode spaced apart by a plurality of materials. A first material may have a memory characteristic exhibited by the first material maintaining a magnitude of an electrically controlled physical property after discontinuing an electrical stimulus on the first material. A second material may have an auxiliary characteristic.

Abstract: Nanoscale switching devices are disclosed. The devices have a first electrode of a nanoscale width; a second electrode of a nanoscale width; and a layer of an active region disposed between and in electrical contact with the first and second electrodes. The active region contains a switching material capable of carrying a significant amount of defects which can trap and de-trap electrons under electrical bias. The switching material is in an amorphous state. A nanoscale crossbar array containing a plurality of the devices and a method for making the devices are also disclosed.

Abstract: An electroforming free memristor includes a first electrode, a second electrode spaced from the first electrode, and a switching layer positioned between the first electrode and the second electrode. The switching layer is formed of a matrix of a switching material and reactive particles that are to react with the switching material during a fabrication process of the memristor to form one or more conductance channels in the switching layer.

Abstract: A reconfigurable multilayer circuit (400) includes a complimentary metal-oxide-semiconductor (CMOS) layer (210) having control circuitry, logic gates (515), and at least two crossbar arrays (205, 420) which overlie the CMOS layer (210). The at least two crossbar arrays (205, 420) are configured by the control circuitry and form reconfigurable interconnections between the logic gates (515) within the CMOS layer (210).