Abstract: A memory device having a scalable bandwidth I/O data bus includes a semiconductor die having a substrate with a first and a second surface. The substrate includes contact pads arranged in rows across the first surface and across the second surface. The contact pads on one surface may be physically arranged in vertical alignment with a corresponding contact pad on the other surface and may be electrically coupled to the corresponding contact pad using a via. The substrate also includes a metallization layer formed on the second surface. The metallization layer includes external data contact pads each arranged in vertical alignment with a respective contact pad on the second surface. Each row of contact pads may be grouped, and the external contact pads within a group are electrically coupled to an adjacent contact pad on the second surface by effectively logically shifting to them to right one contact pad.

Abstract: A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.

Abstract: A portable computer system such as a laptop computer system includes a computing subsystem that includes a processor that may execute instructions that implement application software, and a storage coupled to the processor that may store information. The laptop computer system also includes a wireless subsystem that may communicate with a wireless network. In addition, the wireless subsystem may receive an incoming communication and determine whether a requesting user is an authorized user. The processor may retrieve at least a portion of the information from the storage and send the retrieved information to a destination via email, for example, in response to a request by the requesting user for the information.

Abstract: A system recognizes human beings in their natural environment, without special sensing devices attached to the subjects, uniquely identifies them and tracks them in three dimensional space. The resulting representation is presented directly to applications as a multi-point skeletal model delivered in real-time. The device efficiently tracks humans and their natural movements by understanding the natural mechanics and capabilities of the human muscular-skeletal system. The device also uniquely recognizes individuals in order to allow multiple people to interact with the system via natural movements of their limbs and body as well as voice commands/responses.

Abstract: Techniques for managing a set of states associated with a capture device are disclosed herein. The capture device may detect and bind to users, and may provide feedback about whether the capture device is bound to, or detecting a user. Techniques are also disclosed wherein virtual ports may be associated with users bound to a capture device and feedback about the state of virtual ports may be provided.

Abstract: In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.

Abstract: A system including asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths, for example. The master device may control data transfer between the master device and the slave device. More particularly, the master device may adaptively modify transmit characteristics subsequent to adaptively modifying receiver characteristics based upon information received from the slave device via one or more unidirectional data paths.

Abstract: A portable computer system such as a laptop computer, for example, includes a first processor that may execute instructions corresponding to application software during a first mode of operation. The portable computer system also includes a second processor that may execute the instructions during a second mode of operation. The first processor and the second processor may be heterogeneous processors. Further, operation of the first processor and the second processor in the first mode and the second mode may be dependent upon which of a plurality of system preferences have been selected.

Abstract: A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: A portable computer system such as a laptop computer, for example, includes a first processor that may execute instructions corresponding to application software during a first mode of operation. The portable computer system also includes a second processor that may execute the instructions during a second mode of operation. The first processor and the second processor may be heterogeneous processors. Further, operation of the first processor and the second processor in the first mode and the second mode may be dependent upon which of a plurality of system preferences have been selected.

Abstract: A portable computer system such as a laptop computer, for example, includes a processor and a wireless module. The wireless module may establish a wireless connection to a wireless network and may receive video data such as an MBMS video stream, for example, via one or more wireless channels. The portable computer system also includes a first display and a second display. The second display having a lower resolution than the first display, may display first video images associated with the video data. Upon request by a user of the portable computer system, the wireless module may further receive enhancement video data via one or more additional wireless channels (e.g., side channels) of the wireless connection. The first display may display second video images associated with a combination of the video data and the enhancement video data. The second video images have a higher resolution than the first video images.

Abstract: A portable computer system such as a laptop computer, for example, includes a computing subsystem and a wireless subsystem. The computing subsystem includes a processor that may execute instructions that implement application software. The computing subsystem also includes a memory that is coupled to the processor and may be configured to store the instructions. The wireless subsystem includes a processing unit that may execute instructions and perform functions that are associated with providing a wireless connection to a wireless network such as a wireless telephone network. The processor may execute instructions that may configure and manage operation of the wireless subsystem.

Abstract: A portable computer system such as a laptop computer system includes a processor coupled to a wireless module that may communicate with a computer network via a connection to a wireless network. In addition, portable computer system includes an authentication unit that may be coupled to the wireless module and configured to generate and provide authentication information to the wireless module. The wireless module may be further configured to provide the authentication information to the computer network in response to a challenge from the computer network during a initiation of the connection to the computer network without intervention of the processor. In addition, the wireless module may enable features such as authenticating a remote admin-level user, which may further enable that user to perform security related functions through the wireless module.

Abstract: A portable computer system including wireless communication functionality and global geographic positioning functionality includes a processor coupled to a wireless module, and a global positioning unit coupled to the wireless module and the processor. The wireless module may communicate with a wireless network via a wireless connection. The global positioning unit may be configured to receive geographic location information and to determine a current geographic location of the portable computer system based upon the received geographic location information. The processor may execute system software that may be configured to reconfigure system configuration settings such as security and authentication settings, and system clock settings, for example, dependent upon changes in the current geographic location information. In addition, an authenticated administrative level user may send one or more commands to the wireless module. The commands may cause a system storage to be made unreadable.

Abstract: A portable computer system such as a laptop computer system includes a computing subsystem that includes a processor that may execute instructions that implement application software, and a storage coupled to the processor that may store information. The laptop computer system also includes a wireless subsystem that may communicate with a wireless network. In addition, the wireless subsystem may receive an incoming communication and determine whether a requesting user is an authorized user. The processor may retrieve at least a portion of the information from the storage and send the retrieved information to a destination via email, for example, in response to a request by the requesting user for the information.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: A microprocessor card having a microprocessor is connected to a predetermined pattern of resistors for providing a binary notation signature identifying the speed capability of the microprocessor and for adjusting the speed of the clock signals for the microprocessor. A motherboard having circuitry for recognizing the binary notation signature identifying the speed capability of a microprocessor is connected to the predetermined pattern of resistors. A series of latches latch the microprocessor speed identification into a logic and lookup table circuitry. The table circuitry looks up a binary notation signature correlating the motherboard speed capability with the speed capability of the particular microprocessor. This binary notation signature, which identifies the motherboard speed in relationship to the microprocessor speed, provides the binary notation signature on the resistors and overrides the microprocessor speed identification.

Abstract: The clock configuration of a printed circuit board (PCB) processor card is described. A processor card including a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus is optimized by providing various clock configurations and distributions. In one configuration, multiple clock signals are coupled to a system clock bus for distributing to a host card having system devices. In another configuration, multiple clock signals having various clock rates are coupled to the processor device on the processor card.

Abstract: An apparatus including a system bus coupled to an I/O interface which includes a pointer register and a rejecting circuit which determines whether a write to the pointer register will be accepted or rejected. The I/O interface is further coupled to at least one I/O bus having at least one I/O device connected thereto. The system bus is further coupled to a main memory and to a Central Processing Unit (CPU) which is capable of executing software instructions, providing a command structure corresponding to an access of an I/O device, and writing to the pointer register an address of a location in main memory of the command structure. The CPU further includes a hardware indicator responsive to the rejecting circuit for providing a status signal indicating the status of a write to the pointer register. The CPU executes the software in accordance with the status signal. The apparatus allows the software being executed by the CPU to software pend accesses to devices not directly connected to the system bus.