Abstract: A computer system connector panel including EMI filtering on the computer system housing connector panel instead of on the system motherboard so that I/O signals are filtered just before being transmitted out of the computer system housing thereby reducing EMI affects on external A/V devices.

Abstract: A printed circuit board (PCB) processor card is described. The processor card includes a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus. The processor card is designed to include the elements that are most likely to be upgraded, i.e. the processor and the clock. As such it is particularly useful when employed for system upgrades.

Abstract: The present invention, generally speaking, provides a system and method of decoupling the address and data buses of a system bus using side band information signals. A computer system with which the invention may be used has a system bus including an address bus and a data bus and has, operatively connected to said system bus, multiple master devices, including a microprocessor, and multiple slave devices. In accordance with one embodiment of the invention, the address bus and the data bus are decoupled by providing, in addition to signals carried by the system bus, first side-band signals including, for each master device besides the microprocessor, an address arbitration signal, and providing, in addition to signals carried by the system bus, second side-band signals including, for each slave device, an address termination signal, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus.

Abstract: A method and apparatus for optimizing the performance of a multibus data processing system is provided. An I/O controller is coupled to the I/O bus and includes MORE bit setting means for initiating a MORE stream transaction on the I/O bus and for thereafter terminating the MORE stream transaction. An adapter coupling the I/O bus to the system bus, is configured to receive the MORE stream transaction and transfer it to main memory. The adapter includes MORE bit decoding means for identifying the beginning and the end of the MORE stream transaction, and for identifying whether the MORE stream transaction is a READ or WRITE transaction. The adapter also includes a first buffer for receiving data from the I/O bus and transferring the data to the memory in accordance with the memory's full block transfer size, and a second buffer for receiving a full block of data and transferring that data in accordance with the I/O bus transaction limitations.

Abstract: A method and apparatus for testing complex processor-based computer modules and their associated computer systems by allowing the normal initialization path between a memory component storing code utilized during initialization and the processor to be interrupted and test code from an external test system to be substituted for initialization code. Following initialization, a two-way communication link between the processor and the test system is created to allow interactive testing and status reporting. The testing method and apparatus maximizes the likelihood of precisely identifying defects on the module under test.

Abstract: A computer system includes a plurality of central processing units (CPUs), a main memory, a system control unit (SCU) for controlling the transfer of data between the CPUs and the main memory, and a service processing unit (SPU) to interface the computer system with the outside world, such as an operator console. The method used for interfacing the SPU and SCU includes delivering a BUFFER FULL handshaking signal from the SPU to the SCU in response to the SPU receive buffer having data contained therein and being unavailable to receive data. The SCU responds to the absence of the BUFFER FULL handshaking signal by delivering a TRANSMIT FRAME handshaking signal to the SCU. A preselected duration of time after delivering the transmit frame, the SCU delivers the actual data in a series of fourteen consecutive clock cycles.

Abstract: For efficiently handling data transactions between various system units (CPUs, I/O units and main memory units) in a multi-processor system, the system units are linked via a plurality of expandable crossbar modules, each providing a set of interconnections or well-defined mappings between the sets of input and output nodes, with each output being defined in terms of only one input. In addition to the nodes provided at the input and output sections, each crossbar module is also provided with discrete input and output expansion portions through which the module may be linked to other identically configured crossbar modules when additional nodes are to be integrated into the system. The expansion ports allow serial linking of crossbar modules so as to establish a connection between source and destination nodes which are spread across different crossbar modules.

Abstract: To interface a system control unit with an input/unit in a computer system, an interface includes a transmitter for sequentially transmitting data packets and parity signals between the system control unit and the input/output unit, and a receiver for sequentially receiving the data packets and parity signals. The receiver includes a buffer for storing a plurality of the data packets. The stored data packets are controllably unloaded from the buffer, and a buffer emptied signal is sent back to the transmitter as each data packet is unloaded. The transmitter has a counter which calculates the number of data packets stored in the buffer and asserts a signal that prevents the transmitter from transmitting additional data packets when the buffer becomes full. The receiver compares the parity of the received data packets to the respective parity signals to check for parity errors.