Patents by Inventor Raanan Y. Zehavi

Raanan Y. Zehavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8486835
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 16, 2013
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Tom L. Cadwell, Doris Mytton
  • Patent number: 8476660
    Abstract: A photovoltaic device on a non-semiconductor substrate is disclosed. The device comprises two semiconductor layers forming an active region; at least one of the semiconductor layers is formed by a high-purity plasma spray process; optional layers include one or more barrier layers, a cap layer, a conductive and/or metallization layer, an anti-reflection layer, and distributed Bragg reflector. The device may comprise multiple active regions.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: July 2, 2013
    Assignee: Integrated Photovoltaics, Inc.
    Inventors: Sharone Zehavi, Jerome S. Culik, Raanan Y. Zehavi
  • Publication number: 20130095296
    Abstract: A composite substrate comprising a graphitic layer and a semiconductor layer for a photovoltaic device is disclosed.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 18, 2013
    Applicant: INTEGRATED PHOTOVOLTAIC, INC.
    Inventors: Sharone Zehavi, Raanan Y. Zehavi
  • Publication number: 20130015276
    Abstract: Silicon particles, including powder suitable for plasma spraying semiconductor devices, is formed by milling by a roller mill including silicon rollers and/or plates and having feed and collection systems comprising silicon and operated in a controlled ambient.
    Type: Application
    Filed: October 7, 2011
    Publication date: January 17, 2013
    Applicant: INTEGRATED PHOTOVOLTAIC, INC.
    Inventor: Raanan Y. Zehavi
  • Publication number: 20120252190
    Abstract: The instant invention discloses compositions for source material for a plasma spray gun comprising a Group IV based powder, optionally, a Group IV based liquid, optionally, a gas containing Group IV based gases, optionally a dopant, and a carrier gas, optionally, inert.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Applicant: Integrated Photovoltaics, Inc.
    Inventors: Raanan Y. Zehavi, Sharone Zehavi
  • Patent number: 8153528
    Abstract: The invention relates generally to preparation of a substrate for use in a photovoltaic device by application of a filling material and subsequent planarization of the top surface; optionally, a barrier layer is added.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: April 10, 2012
    Assignee: Integrated Photovoltaic, Inc.
    Inventors: Larry Hendler, Sharone Zehavi, Tanya Dulkin, Raanan Y. Zehavi
  • Publication number: 20110192461
    Abstract: A solar cell comprises a recrystallized active layer wherein the active layer has preferred characteristics.
    Type: Application
    Filed: January 20, 2011
    Publication date: August 11, 2011
    Applicant: INTEGRATED PHOTOVOLTAIC, INC.
    Inventors: Larry Hendler, Sharone Zehavi, Tanya Dulkin, Raanan Y. Zehavi
  • Publication number: 20110189405
    Abstract: The instant invention discloses a method of generating silicon powder aerosol to maintain cleanliness of the silicon powder during the feed process which utilizes an carrier gas, optionally, inert, and non-contaminating feed line to a plasma spray gun.
    Type: Application
    Filed: February 2, 2011
    Publication date: August 4, 2011
    Applicant: INTEGRATED PHOTOVOLTAIC, INC.
    Inventors: Raanan Y. Zehavi, Sharone Zehavi
  • Publication number: 20110041903
    Abstract: A photovoltaic device on a non-semiconductor substrate is disclosed. The device comprises two semiconductor layers forming an active region; at least one of the semiconductor layers is formed by a high-purity plasma spray process; optional layers include one or more barrier layers, a cap layer, a conductive and/or metallization layer, an anti-reflection layer, and distributed Bragg reflector. The device may comprise multiple active regions.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 24, 2011
    Applicant: Integrated Photovoltaic, Inc.
    Inventors: Sharone Zehavi, Jerome S. Culik, Raanan Y. Zehavi
  • Publication number: 20100009123
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Application
    Filed: September 18, 2009
    Publication date: January 14, 2010
    Applicant: INTEGRATED MATERIALS, INC.
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Robert W. Mytton, Doris Mytton, Tom L. Cadwell
  • Patent number: 7611989
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: November 3, 2009
    Assignee: Integrated Materials, Inc.
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Robert W. Mytton, Doris Mytton, legal representative, Tom L. Cadwell
  • Publication number: 20080220558
    Abstract: A plasma spray gun configured to spray semiconductor grade silicon to form semiconductor structures including p-n junctions includes silicon parts such as the cathode or anode or other parts facing the plasma or carrying the silicon powder having at least surface portions formed of high purity silicon. The semiconductor dopant may be included in the sprayed silicon.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 11, 2008
    Applicant: Integrated Photovoltaics, Inc.
    Inventors: Raanan Y. Zehavi, James E. Boyle
  • Publication number: 20080152805
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 26, 2008
    Applicant: INTEGRATED MATERIALS, INC.
    Inventors: James E. BOYLE, Reese REYNOLDS, Raanan Y. ZEHAVI, Robert W. MYTTON, Tom L. CADWELL, Doris MYTTON
  • Patent number: 6979659
    Abstract: A process for hydrogen annealing silicon wafers that have been cut from an ingot and polished on both sides, thereby removing crystal originated pits (COPs) in their surface. The wafers are then stacked in a tower having at least support surfaces made from virgin polysilicon, that is, polysilicon form by chemical vapor deposition, preferably from monosilane. The tower may include four virgin polysilicon legs have support teeth slotted at inclined angles along the legs and fixed at their opposed ends to bases. The wafers so supported on the virgin polysilicon towers are annealed in a hydrogen ambient at 1250° C. for 12 hours.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: December 27, 2005
    Assignee: Integrated Materials, Inc.
    Inventors: Raanan Y. Zehavi, James E. Boyle, Laurence D. Delaney
  • Patent number: 6838636
    Abstract: A method of welding two silicon workpieces (20, 22) together into one member without the formation of cracks along the weld. A first method passes current (34, 36) through one or both of the workpieces to heat them to between 600 and 900° C. Then an electric, laser, or plasma welder (38, 40) passes along the seam (24) between the workpieces to weld them together. A second method passing current (34) through a plate (60), preferably formed of silicon, which either supports the workpieces or is brought into contact with at least one of them, whereby the workpieces are preheated prior to the welding operation.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: January 4, 2005
    Assignee: Integrated Materials, Inc.
    Inventors: Raanan Y. Zehavi, Robert L. Davis, David B. Ackard, James W. Govorko
  • Publication number: 20040197974
    Abstract: A process for hydrogen annealing silicon wafers that have been cut from an ingot and polished on both sides, thereby removing crystal originated pits (COPs) in their surface. The wafers are then stacked in a tower having at least support surfaces made from virgin polysilicon, that is, polysilicon form by chemical vapor deposition, preferably from monosilane. The tower may include four virgin polysilicon legs have support teeth slotted at inclined angles along the legs and fixed at their opposed ends to bases. The wafers so supported on the virgin polysilicon towers are annealed in a hydrogen ambient at 1250° C. for 12 hours.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 7, 2004
    Inventors: Raanan Y. Zehavi, James E. Boyle, Laurence D. Delaney
  • Patent number: 6727191
    Abstract: A process for hydrogen annealing silicon wafers that have been cut from an ingot and polished on both sides, thereby removing crystal originated pits (COPs) in their surface. The wafers are then stacked in a tower having at least support surfaces made from virgin polysilicon, that is, polysilicon form by chemical vapor deposition, preferably from monosilane. The tower may include four virgin polysilicon legs have support teeth slotted along the legs and fixed at their opposed ends to bases. The wafers are supported at four equally distributed points at 0.707 of the wafer radius. The wafers so supported on the virgin polysilicon towers are annealed in a hydrogen ambient at 1250° C. for 12 hours.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: April 27, 2004
    Assignee: Integrated Materials, Inc.
    Inventors: Raanan Y. Zehavi, James E. Boyle, Laurence D. Delaney
  • Publication number: 20040040885
    Abstract: A silicon tower for removably supporting a plurality of silicon wafers during thermal processing. A tower includes plural silicon legs secured on their ends to two bases. A plurality of slots are cut in the legs allowing slidable insertion of the wafers and support for them. Preferably, the teeth incline upwardly at 1-3° and have horizontal support areas polished on their ends. Preferably, the legs are machined from virgin polysilicon formed by chemical vapor deposition from silane. The bases may be either virgin poly or monocrystalline silicon and be either integral or composed of multiple parts. Virgin polysilicon is preferably annealed to above 1025° C. before machining. Silicon parts may be joined by applying a spin-on glass between the parts and annealing the assembly.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 4, 2004
    Inventors: James E. Boyle, Robert L. Davis, Laurence D. Delaney, Raanan Y. Zehavi
  • Publication number: 20030213785
    Abstract: A method of welding two silicon workpieces (20, 22) together into one member without the formation of cracks along the weld. A first method passes current (34, 36) through one or both of the workpieces to heat them to between 600 and 900° C. Then an electric, laser, or plasma welder (38, 40) passes along the seam (24) between the workpieces to weld them together. A second method passing current (34) through a plate (60), preferably formed of silicon, which either supports the workpieces or is brought into contact with at least one of them, whereby the workpieces are preheated prior to the welding operation.
    Type: Application
    Filed: June 18, 2003
    Publication date: November 20, 2003
    Inventors: Raanan Y. Zehavi, Robert L. Davis, David B. Ackard, James W. Govorko
  • Patent number: 6617225
    Abstract: A method of fabricating parts of silicon, preferably virgin polysilicon formed by chemical vapor deposition of silane, and assembling them into a complex structure, such as a silicon tower or boat for removably supporting a plurality of silicon wafers during thermal processing. The virgin polysilicon is annealed to above 1025° C. before it is machined into a predetermined shape. After machining, the silicon parts are annealed in an oxygen ambient. The machined parts are then assembled and joined together followed by another anneal of the assembled structure. A preferred embodiment of the tower includes four legs secured on their ends to two bases. A plurality of slots are cut in the legs allowing slidable insertion of the wafers and support for them. The bases may be either virgin poly or monocrystalline silicon and be either integral or composed of multiple parts.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: September 9, 2003
    Assignee: Integrated Materials, Inc.
    Inventors: James E. Boyle, Robert L. Davis, Laurence D. Delaney, Raanan Y. Zehavi