Patents by Inventor Raanan Y. Zehavi
Raanan Y. Zehavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8486835Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.Type: GrantFiled: September 18, 2009Date of Patent: July 16, 2013Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Tom L. Cadwell, Doris Mytton
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Patent number: 8476660Abstract: A photovoltaic device on a non-semiconductor substrate is disclosed. The device comprises two semiconductor layers forming an active region; at least one of the semiconductor layers is formed by a high-purity plasma spray process; optional layers include one or more barrier layers, a cap layer, a conductive and/or metallization layer, an anti-reflection layer, and distributed Bragg reflector. The device may comprise multiple active regions.Type: GrantFiled: August 20, 2010Date of Patent: July 2, 2013Assignee: Integrated Photovoltaics, Inc.Inventors: Sharone Zehavi, Jerome S. Culik, Raanan Y. Zehavi
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Publication number: 20130095296Abstract: A composite substrate comprising a graphitic layer and a semiconductor layer for a photovoltaic device is disclosed.Type: ApplicationFiled: October 12, 2011Publication date: April 18, 2013Applicant: INTEGRATED PHOTOVOLTAIC, INC.Inventors: Sharone Zehavi, Raanan Y. Zehavi
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Publication number: 20130015276Abstract: Silicon particles, including powder suitable for plasma spraying semiconductor devices, is formed by milling by a roller mill including silicon rollers and/or plates and having feed and collection systems comprising silicon and operated in a controlled ambient.Type: ApplicationFiled: October 7, 2011Publication date: January 17, 2013Applicant: INTEGRATED PHOTOVOLTAIC, INC.Inventor: Raanan Y. Zehavi
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Publication number: 20120252190Abstract: The instant invention discloses compositions for source material for a plasma spray gun comprising a Group IV based powder, optionally, a Group IV based liquid, optionally, a gas containing Group IV based gases, optionally a dopant, and a carrier gas, optionally, inert.Type: ApplicationFiled: March 28, 2011Publication date: October 4, 2012Applicant: Integrated Photovoltaics, Inc.Inventors: Raanan Y. Zehavi, Sharone Zehavi
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Patent number: 8153528Abstract: The invention relates generally to preparation of a substrate for use in a photovoltaic device by application of a filling material and subsequent planarization of the top surface; optionally, a barrier layer is added.Type: GrantFiled: November 19, 2010Date of Patent: April 10, 2012Assignee: Integrated Photovoltaic, Inc.Inventors: Larry Hendler, Sharone Zehavi, Tanya Dulkin, Raanan Y. Zehavi
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Publication number: 20110192461Abstract: A solar cell comprises a recrystallized active layer wherein the active layer has preferred characteristics.Type: ApplicationFiled: January 20, 2011Publication date: August 11, 2011Applicant: INTEGRATED PHOTOVOLTAIC, INC.Inventors: Larry Hendler, Sharone Zehavi, Tanya Dulkin, Raanan Y. Zehavi
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Publication number: 20110189405Abstract: The instant invention discloses a method of generating silicon powder aerosol to maintain cleanliness of the silicon powder during the feed process which utilizes an carrier gas, optionally, inert, and non-contaminating feed line to a plasma spray gun.Type: ApplicationFiled: February 2, 2011Publication date: August 4, 2011Applicant: INTEGRATED PHOTOVOLTAIC, INC.Inventors: Raanan Y. Zehavi, Sharone Zehavi
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Publication number: 20110041903Abstract: A photovoltaic device on a non-semiconductor substrate is disclosed. The device comprises two semiconductor layers forming an active region; at least one of the semiconductor layers is formed by a high-purity plasma spray process; optional layers include one or more barrier layers, a cap layer, a conductive and/or metallization layer, an anti-reflection layer, and distributed Bragg reflector. The device may comprise multiple active regions.Type: ApplicationFiled: August 20, 2010Publication date: February 24, 2011Applicant: Integrated Photovoltaic, Inc.Inventors: Sharone Zehavi, Jerome S. Culik, Raanan Y. Zehavi
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Publication number: 20100009123Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.Type: ApplicationFiled: September 18, 2009Publication date: January 14, 2010Applicant: INTEGRATED MATERIALS, INC.Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Robert W. Mytton, Doris Mytton, Tom L. Cadwell
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Patent number: 7611989Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.Type: GrantFiled: December 18, 2007Date of Patent: November 3, 2009Assignee: Integrated Materials, Inc.Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Robert W. Mytton, Doris Mytton, legal representative, Tom L. Cadwell
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Publication number: 20080220558Abstract: A plasma spray gun configured to spray semiconductor grade silicon to form semiconductor structures including p-n junctions includes silicon parts such as the cathode or anode or other parts facing the plasma or carrying the silicon powder having at least surface portions formed of high purity silicon. The semiconductor dopant may be included in the sprayed silicon.Type: ApplicationFiled: March 5, 2008Publication date: September 11, 2008Applicant: Integrated Photovoltaics, Inc.Inventors: Raanan Y. Zehavi, James E. Boyle
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Publication number: 20080152805Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.Type: ApplicationFiled: December 18, 2007Publication date: June 26, 2008Applicant: INTEGRATED MATERIALS, INC.Inventors: James E. BOYLE, Reese REYNOLDS, Raanan Y. ZEHAVI, Robert W. MYTTON, Tom L. CADWELL, Doris MYTTON
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Patent number: 6979659Abstract: A process for hydrogen annealing silicon wafers that have been cut from an ingot and polished on both sides, thereby removing crystal originated pits (COPs) in their surface. The wafers are then stacked in a tower having at least support surfaces made from virgin polysilicon, that is, polysilicon form by chemical vapor deposition, preferably from monosilane. The tower may include four virgin polysilicon legs have support teeth slotted at inclined angles along the legs and fixed at their opposed ends to bases. The wafers so supported on the virgin polysilicon towers are annealed in a hydrogen ambient at 1250° C. for 12 hours.Type: GrantFiled: April 22, 2004Date of Patent: December 27, 2005Assignee: Integrated Materials, Inc.Inventors: Raanan Y. Zehavi, James E. Boyle, Laurence D. Delaney
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Patent number: 6838636Abstract: A method of welding two silicon workpieces (20, 22) together into one member without the formation of cracks along the weld. A first method passes current (34, 36) through one or both of the workpieces to heat them to between 600 and 900° C. Then an electric, laser, or plasma welder (38, 40) passes along the seam (24) between the workpieces to weld them together. A second method passing current (34) through a plate (60), preferably formed of silicon, which either supports the workpieces or is brought into contact with at least one of them, whereby the workpieces are preheated prior to the welding operation.Type: GrantFiled: June 18, 2003Date of Patent: January 4, 2005Assignee: Integrated Materials, Inc.Inventors: Raanan Y. Zehavi, Robert L. Davis, David B. Ackard, James W. Govorko
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Publication number: 20040197974Abstract: A process for hydrogen annealing silicon wafers that have been cut from an ingot and polished on both sides, thereby removing crystal originated pits (COPs) in their surface. The wafers are then stacked in a tower having at least support surfaces made from virgin polysilicon, that is, polysilicon form by chemical vapor deposition, preferably from monosilane. The tower may include four virgin polysilicon legs have support teeth slotted at inclined angles along the legs and fixed at their opposed ends to bases. The wafers so supported on the virgin polysilicon towers are annealed in a hydrogen ambient at 1250° C. for 12 hours.Type: ApplicationFiled: April 22, 2004Publication date: October 7, 2004Inventors: Raanan Y. Zehavi, James E. Boyle, Laurence D. Delaney
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Patent number: 6727191Abstract: A process for hydrogen annealing silicon wafers that have been cut from an ingot and polished on both sides, thereby removing crystal originated pits (COPs) in their surface. The wafers are then stacked in a tower having at least support surfaces made from virgin polysilicon, that is, polysilicon form by chemical vapor deposition, preferably from monosilane. The tower may include four virgin polysilicon legs have support teeth slotted along the legs and fixed at their opposed ends to bases. The wafers are supported at four equally distributed points at 0.707 of the wafer radius. The wafers so supported on the virgin polysilicon towers are annealed in a hydrogen ambient at 1250° C. for 12 hours.Type: GrantFiled: February 26, 2001Date of Patent: April 27, 2004Assignee: Integrated Materials, Inc.Inventors: Raanan Y. Zehavi, James E. Boyle, Laurence D. Delaney
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Publication number: 20040040885Abstract: A silicon tower for removably supporting a plurality of silicon wafers during thermal processing. A tower includes plural silicon legs secured on their ends to two bases. A plurality of slots are cut in the legs allowing slidable insertion of the wafers and support for them. Preferably, the teeth incline upwardly at 1-3° and have horizontal support areas polished on their ends. Preferably, the legs are machined from virgin polysilicon formed by chemical vapor deposition from silane. The bases may be either virgin poly or monocrystalline silicon and be either integral or composed of multiple parts. Virgin polysilicon is preferably annealed to above 1025° C. before machining. Silicon parts may be joined by applying a spin-on glass between the parts and annealing the assembly.Type: ApplicationFiled: August 29, 2003Publication date: March 4, 2004Inventors: James E. Boyle, Robert L. Davis, Laurence D. Delaney, Raanan Y. Zehavi
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Publication number: 20030213785Abstract: A method of welding two silicon workpieces (20, 22) together into one member without the formation of cracks along the weld. A first method passes current (34, 36) through one or both of the workpieces to heat them to between 600 and 900° C. Then an electric, laser, or plasma welder (38, 40) passes along the seam (24) between the workpieces to weld them together. A second method passing current (34) through a plate (60), preferably formed of silicon, which either supports the workpieces or is brought into contact with at least one of them, whereby the workpieces are preheated prior to the welding operation.Type: ApplicationFiled: June 18, 2003Publication date: November 20, 2003Inventors: Raanan Y. Zehavi, Robert L. Davis, David B. Ackard, James W. Govorko
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Patent number: 6617225Abstract: A method of fabricating parts of silicon, preferably virgin polysilicon formed by chemical vapor deposition of silane, and assembling them into a complex structure, such as a silicon tower or boat for removably supporting a plurality of silicon wafers during thermal processing. The virgin polysilicon is annealed to above 1025° C. before it is machined into a predetermined shape. After machining, the silicon parts are annealed in an oxygen ambient. The machined parts are then assembled and joined together followed by another anneal of the assembled structure. A preferred embodiment of the tower includes four legs secured on their ends to two bases. A plurality of slots are cut in the legs allowing slidable insertion of the wafers and support for them. The bases may be either virgin poly or monocrystalline silicon and be either integral or composed of multiple parts.Type: GrantFiled: August 22, 2002Date of Patent: September 9, 2003Assignee: Integrated Materials, Inc.Inventors: James E. Boyle, Robert L. Davis, Laurence D. Delaney, Raanan Y. Zehavi