Patents by Inventor Rabindra N. Das

Rabindra N. Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418350
    Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 17, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Patent number: 10396269
    Abstract: A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 27, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
  • Patent number: 10381541
    Abstract: A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 13, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Eric A. Dauler
  • Patent number: 10242968
    Abstract: A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 26, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Eric A. Dauler
  • Patent number: 10229897
    Abstract: A multi-layer semiconductor device (or structure) includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces. Additionally, each of the at least two semiconductor structures includes a first section having first and second opposing surfaces and a plurality of electrical connections extending between select portions of the first and second surfaces. Each of the at least two semiconductor structures also includes a second section having first and second opposing surfaces, with the first surface of the second section disposed over and coupled to the second surface of the first section. Methods for fabricating a multi-layer semiconductor structure from a plurality of semiconductor structures are also provided.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 12, 2019
    Assignee: Massachusetts Institute of Technology
    Inventor: Rabindra N. Das
  • Patent number: 10199553
    Abstract: Described are concepts, systems, circuits and techniques related to shielded through via structures and methods for fabricating such shielded through via structures. The described shielded through via structures and techniques allow for assembly of multi-layer semiconductor structures including one or more superconducting semiconductor structures (or integrated circuits).
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: February 5, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
  • Patent number: 10134972
    Abstract: A cryogenic quantum bit package with multiple qubit circuits facilitates inter-qubit signal propagation using a multi-chip module (MCM). Multiple qubits are grouped within the package into one or more qubit integrated circuits (ICs). The qubit ICs themselves are electrically coupled to each other via a structure including a superconducting MCM and superconducting interconnects. Coupling of quantum electrical signals between a qubit and other qubits, a substrate, or the MCM uses a coupler circuit, such as a Josephson junction, capacitor, inductor, or resonator.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 20, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
  • Patent number: 10121754
    Abstract: A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 6, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
  • Patent number: 10079224
    Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corresponding method for fabricating a semiconductor structure is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 18, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Publication number: 20180247974
    Abstract: A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called “device”) is provided as a substantially high quality factor, low loss superconducting device.
    Type: Application
    Filed: July 21, 2016
    Publication date: August 30, 2018
    Inventors: William D. Oliver, Rabindra N. Das, David J. Hover, Danna Rosenberg, Xhovalin Miloshi, Vladimir Bolkhovsky, Jonilyn L. Yoder, Corey W. Stull, Mark A. Gouker
  • Publication number: 20180102469
    Abstract: A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.
    Type: Application
    Filed: August 23, 2017
    Publication date: April 12, 2018
    Inventors: Rabindra N. Das, Eric A. Dauler
  • Publication number: 20180102470
    Abstract: A cryogenic electronic package includes a circuitized substrate, an interposer, a superconducting multichip module (SMCM) and at least one superconducting semiconductor structure. The at least one superconducting semiconductor structure is disposed over and coupled to the SMCM, and the interposer is disposed between the SMCM and the substrate. The SMCM and the at least one superconducting semiconductor structure are electrically coupled to the substrate through the interposer. A cryogenic electronic assembly including a plurality of cryogenic electronic packages is also provided.
    Type: Application
    Filed: August 23, 2017
    Publication date: April 12, 2018
    Inventors: Rabindra N. Das, Eric A. Dauler
  • Patent number: 9881904
    Abstract: A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The electrical connections correspond to first conductive structures. The multi-layer semiconductor device also includes one or more second conductive structures which are provided as through oxide via (TOV) or through insulator via (TIV) structures. The multi-layer semiconductor device additionally includes one or more silicon layers. At least a first one of the silicon layers includes at least one third conductive structure which is provided as a through silicon via (TSV) structure. The multi-layer semiconductor device further includes one or more via joining layers including at least one fourth conductive structure. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: January 30, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Mark A. Gouker, Pascale Gouker, Leonard M. Johnson, Ryan C. Johnson
  • Publication number: 20180013052
    Abstract: Quantum bit (qubit) circuits, coupler circuit structures and coupling techniques are described. Such circuits and techniques may be used to provide multi-qubit circuits suitable for use in multichip modules (MCMs).
    Type: Application
    Filed: November 3, 2016
    Publication date: January 11, 2018
    Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
  • Publication number: 20180012932
    Abstract: A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.
    Type: Application
    Filed: November 3, 2016
    Publication date: January 11, 2018
    Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
  • Publication number: 20170373044
    Abstract: A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 28, 2017
    Inventors: Rabindra N. Das, Eric A. Dauler
  • Patent number: 9812429
    Abstract: A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: November 7, 2017
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Rabindra N. Das, Mark A. Gouker, Pascale Gouker, Leonard M. Johnson, Ryan C. Johnson
  • Patent number: 9786633
    Abstract: A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 10, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Peter G. Murphy, Karen E. Magoon, Noyan Kinayman, Michael J. Barbieri, Timothy M. Hancock, Mark A. Gouker
  • Patent number: 9780075
    Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 3, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Patent number: 9756724
    Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: September 5, 2017
    Inventors: Rabindra N. Das, Kostas I. Papathomas, Voya R. Markovich