Patents by Inventor Radu M. Secareanu
Radu M. Secareanu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9048110Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.Type: GrantFiled: March 13, 2013Date of Patent: June 2, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
-
Patent number: 8957496Abstract: An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.Type: GrantFiled: April 17, 2013Date of Patent: February 17, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Qiang Li, Olin L. Hartin, Sateh Jalaleddine, Radu M. Secareanu, Michael J. Zunino
-
Publication number: 20140312457Abstract: An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.Type: ApplicationFiled: April 17, 2013Publication date: October 23, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Qiang Li, Olin L. Hartin, Sateh Jalaleddine, Radu M. Secareanu, Michael J. Zunino
-
Publication number: 20130207229Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.Type: ApplicationFiled: March 13, 2013Publication date: August 15, 2013Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
-
Patent number: 7834428Abstract: Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground rail (255) is coupled to the source and substrate tie (2224), and a ground rail (285) is coupled to substrate tie (2250). Ground rails (255) and (285) are configured to be coupled to different ground networks (250 and 280). One method includes producing a model of a semiconductor device including a standard semiconductor cell (710). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (720), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell (730).Type: GrantFiled: February 28, 2007Date of Patent: November 16, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Radu M. Secareanu, Olin L. Hartin, Emre Salman
-
Patent number: 7683483Abstract: Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93) or form a cross with the device cell (43, 73, 83, 93) at the intersection of the cross. The bumps (42, 72, 82) are desirably spaced apart by the minimum allowable bump (42, 72, 82) pitch (Lm). Typically, each device cell (43, 73, 83, 93) contains one or more active device regions (44, 74, 86, 96) depending on the overall function. Complex devices (40, 70) are formed by an X-Y array of the clusters (46), where adjacent clusters (46) may share bumps (43, 73, 83, 93) and/or device cells (43, 73, 83, 93). In a preferred embodiment, the bumps (42, 82) form the outer perimeter (48) of the device (40, 80, 90). The maximum device temperature and overall noise is reduced.Type: GrantFiled: February 5, 2007Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Sandra J. Wipf
-
Publication number: 20090302440Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.Type: ApplicationFiled: July 30, 2009Publication date: December 10, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
-
Patent number: 7608913Abstract: An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.Type: GrantFiled: February 23, 2006Date of Patent: October 27, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
-
Patent number: 7595679Abstract: A system-on-chip or other circuit has an on-chip noise-free ground which is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, can be provided to add an additional low impedance ground path.Type: GrantFiled: April 12, 2006Date of Patent: September 29, 2009Assignee: University of RochesterInventors: Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
-
Publication number: 20080203494Abstract: Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground rail (255) is coupled to the source and substrate tie (2224), and a ground rail (285) is coupled to substrate tie (2250). Ground rails (255) and (285) are configured to be coupled to different ground networks (250 and 280). One method includes producing a model of a semiconductor device including a standard semiconductor cell (710). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (720), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell (730).Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Radu M. Secareanu, Olin L. Hartin, Emre Salman
-
Publication number: 20080185686Abstract: Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93) or form a cross with the device cell (43, 73, 83, 93) at the intersection of the cross. The bumps (42, 72, 82) are desirably spaced apart by the minimum allowable bump (42, 72, 82) pitch (Lm). Typically, each device cell (43, 73, 83, 93) contains one or more active device regions (44, 74, 86, 96) depending on the overall function. Complex devices (40, 70) are formed by an X-Y array of the clusters (46), where adjacent clusters (46) may share bumps (43, 73, 83, 93) and/or device cells (43, 73, 83, 93). In a preferred embodiment, the bumps (42, 82) form the outer perimeter (48) of the device (40, 80, 90). The maximum device temperature and overall noise is reduced.Type: ApplicationFiled: February 5, 2007Publication date: August 7, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Sandra J. Wipf
-
Patent number: 7138686Abstract: A system-on chip (SOC) (100) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks (120, 220) and ESD protected pads (302, 304, 306, 308, 310, 312, and 314). A VDD isolation pad (302) is connected to an N well ring (124) of the first noise sensitive circuit (120) to collect noise from the substrate (110) and isolate the circuit from the P well region (112). A ground protected pad (304) is connected to an isolated P well (126) of a first noise sensitive circuit (120). The ground pad (304) collects noise from the isolated P well (126) and sends it to ground. A dedicated ground isolation pad (306) is connected to a P well ring (224) of a second noise sensitive circuit (220). The dedicated ground isolation pad (306) collects noise from the P well ring (224) and sends it to ground.Type: GrantFiled: May 31, 2005Date of Patent: November 21, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Suman K. Banerjee, Enrique Ferrer, Olin L. Hartin, Radu M. Secareanu
-
Patent number: 6788134Abstract: A current generator circuit and method capable of operating with a power supply voltage of less than two VT utilizing a reference transistor and a buffer transistor, each transistor having a source, a drain, and a gate, the drain of the reference transistor coupled to the source of the buffer transistor, the drain of the buffer transistor adapted to be coupled to a power supply, a bias circuit coupled to the drain of the reference transistor and the source of the buffer transistor, and an amplifier coupled to the bias circuit to provide a feedback voltage substantially independent of the voltage of the power supply and sufficient to maintain the reference transistor in constant bias.Type: GrantFiled: December 20, 2002Date of Patent: September 7, 2004Assignee: Freescale Semiconductor, Inc.Inventor: Radu M. Secareanu
-
Publication number: 20040119527Abstract: A current generator circuit and method capable of operating with a power supply voltage of less than two VT utilizing a reference transistor and a buffer transistor, each transistor having a source, a drain, and a gate, the drain of the reference transistor coupled to the source of the buffer transistor, the drain of the buffer transistor adapted to be coupled to a power supply, a bias circuit coupled to the drain of the reference transistor and the source of the buffer transistor, and an amplifier coupled to the bias circuit to provide a feedback voltage substantially independent of the voltage of the power supply and sufficient to maintain the reference transistor in constant bias.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventor: Radu M. Secareanu
-
Patent number: 6366127Abstract: CMOS voltage interface circuits have low power consumption, and minimal delays and power dissipation for the driving strength of the output. The circuits use a interface block which is operative upon the applied input signal, depending upon its state and timing, to generate the output at a specified voltage level which may be different from the level of the applied input.Type: GrantFiled: April 27, 2000Date of Patent: April 2, 2002Assignee: The University of RochesterInventors: Eby Friedman, Radu M. Secareanu
-
Patent number: 6166590Abstract: Circuit useful as current mirror and/or current divider has a circuit topology containing mirror and reference transistor pairs, respectively provided by MOS P and N type transistors for the up and down mirrors. The mirror transistor in each pair is followed by a buffer transistor which provides the current output. The topology obtains equal input and output currents through the DC biasing of the reference and mirror transistors by providing equality of the D to S and G to S voltages operative in both the reference and mirror transistors of both mirrors. The topology provides matched performance for the up and down current mirrors with very high mirroring accuracy, design insensitive up and down mirrored current, excellent operation over a wide power supply range, temperature insensitive precision, and the possibility of conveniently obtaining a wide range of current divisions.Type: GrantFiled: May 14, 1999Date of Patent: December 26, 2000Assignee: The University of RochesterInventors: Eby Friedman, Radu M. Secareanu
-
Patent number: 6163174Abstract: CMOS buffer circuits are provided having multiple stages of driving transistors defining a fast "1" data path and a fast "0" data path for transmitting data signals from the input to output of the buffer. Each stage before the last stage in each of the data paths has at least one nulling transistor coupled to the driving transistor of the stage. Separate from the data paths, the nulling transistors of each data path are operated to synchronously null the driving transistors of the data path to prepare such driving transistors for the next fast transition in the input data signal. Another nulling transistor may be also coupled to the driving transistor of each stage before the last stage of each data path which prevents the data path from floating when the data path is not transmitting a transition of the input signal to output of the buffer.Type: GrantFiled: May 25, 1999Date of Patent: December 19, 2000Assignee: The University of RochesterInventors: Eby Friedman, Radu M. Secareanu