NOISE ISOLATION BETWEEN CIRCUIT BLOCKS IN AN INTEGRATED CIRCUIT CHIP
An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
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This application is a divisional of co-pending U.S. patent application Ser. No. 11/360,285, filed on Feb. 23, 2006.
TECHNICAL FIELDEmbodiments relate in general to integrated circuits and more specifically to noise isolation between circuit blocks in an integrated circuit chip.
BACKGROUNDIncreasingly, integrated circuit chips have different types of circuit blocks, such as analog and digital circuit blocks. Without proper noise isolation, noise generated by digital circuit blocks can interfere with more sensitive circuit blocks, such as phase locked loops and low noise amplifier circuits. Conventional noise isolation between different types of circuit blocks requires bias. Bias, however, is prone to contamination and thus compromises noise isolation efficiency.
Thus, there is a need for improved noise isolation between circuit blocks in an integrated circuit chip.
Embodiments of the inventive subject matter may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments.
DETAILED DESCRIPTIONThe following sets forth a detailed description of a mode for carrying out the embodiments of the inventive subject matter. The description is intended to be illustrative of the embodiments and should not be taken to be limiting.
In one aspect, an integrated circuit, including a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block, is provided. The integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block.
In another aspect, an integrated circuit, including a p-well block region formed in a substrate by blocking insertion of any dopants in a region of the substrate for providing noise isolation between a first circuit block and a second circuit block, is provided. The integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block. The integrated circuit further includes a first grounded highly doped region formed between the guard region and the first circuit block and a second grounded highly doped region formed between the guard region and the second circuit block. The integrated circuit further includes a grounded conductive shield formed over a dielectric layer formed at least over the p-well block region and the guard region.
In yet another aspect, an integrated circuit including a p-well block region formed in a substrate by blocking insertion of any dopants in a region of the substrate for providing noise isolation between a first circuit block and a second circuit block, is provided. The integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block. The integrated circuit further includes a first grounded highly doped region formed between the guard region and the first circuit block and a second grounded highly doped region formed between the guard region and the second circuit block. The integrated circuit further includes a grounded conductive shield formed over a dielectric layer formed at least over the p-well block region and the guard region. The integrated circuit further includes a trench formed between the p-well block region and the guard region.
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In the foregoing specification, specific embodiments have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the inventive subject matter as set forth in the claims below. For example, although the p-well block region has been described as placed between two circuit blocks to provide noise isolation between the two circuit blocks, p-well block region may also be placed between ESD pads or digital pads. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the inventive subject matter.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims
1. An integrated circuit, comprising:
- a first circuit block formed in a substrate;
- a second circuit block formed in the substrate; and
- a plurality of regions formed between the first circuit block and the second circuit block, wherein the plurality of regions are configured to provide noise isolation between the first circuit block and the second circuit block, and the plurality of regions includes:
- a p-well block region formed in the substrate, which has a first doping concentration of a p-type dopant, wherein the p-well block region is a ring formed so that at least a portion of the ring is positioned between the first circuit block and the second circuit block, and wherein the p-well block region does not include any active region therein,
- a first portion of a guard region formed in the substrate between the p-well block region and the first circuit block, wherein the first portion of the guard region has a second doping concentration of a p-type dopant,
- a second portion of the guard region formed in the substrate between the p-well block region and the second circuit block, wherein the second portion of the guard region has the second doping concentration,
- a first grounded highly doped region formed in the substrate between the first portion of the guard region and the first circuit block, wherein the first grounded highly doped region has a third doping concentration of a p-type dopant, and
- a second grounded highly doped region formed in the substrate between the second portion of the guard region and the second circuit block, wherein the second grounded highly doped region has the third doping concentration, and wherein the second doping concentration is higher than the first doping concentration, and the third doping concentration is higher than the second doping concentration.
2. The integrated circuit of claim 1, wherein the p-well block region is a ring formed surrounding the first circuit block.
3. The integrated circuit of claim 1, wherein the first portion of the guard region is a ring formed surrounding the first circuit block.
4. The integrated circuit of claim 1, wherein the first portion of the guard region is a ring formed surrounding the p-well block region.
5. The integrated circuit of claim 1, further comprising a first trench formed between the p-well block region and the first portion of the guard region.
6. The integrated circuit of claim 5, wherein the first trench has a depth substantially deeper than the p-well block region and the first portion of the guard region.
7. The integrated circuit of claim 5, further comprising a second trench formed between the p-well block region and the second portion of the guard region.
8. The integrated circuit of claim 7, wherein the second trench has a depth substantially deeper than the p-well block region and the second portion of the guard region.
9. The integrated circuit of claim 1, further comprising:
- a dielectric layer formed at least over the p-well block region and the first and second portions of the guard region; and
- a grounded conductive shield formed over the dielectric layer.
10. The integrated circuit of claim 9, wherein the grounded conductive shield is positioned such that an area occupied by the grounded conductive shield over the first circuit block is different from an area occupied by the grounded conductive shield over the second circuit block.
11. The integrated circuit of claim 1, further comprising:
- at least one interconnect connecting the first circuit block to the second circuit block, which is formed at a greater distance from a top surface of the substrate in a region directly above the p-well block region than other regions above the substrate.
12. An integrated circuit, comprising:
- a first circuit block formed in a substrate;
- a second circuit block formed in the substrate;
- a plurality of regions formed between the first circuit block and the second circuit block, wherein the plurality of regions are configured to provide noise isolation between the first circuit block and the second circuit block, and the plurality of regions includes:
- a p-well block region formed in the substrate, which has a first doping concentration of a p-type dopant, wherein the p-well block region is at least partially positioned between the first circuit block and the second circuit block, and wherein the p-well block region does not include any active region therein,
- a first portion of a guard region formed in the substrate between the p-well block region and the first circuit block, wherein the first portion of the guard region has a second doping concentration of a p-type dopant,
- a first trench formed between the p-well block region and the first portion of the guard region,
- a first grounded highly doped region formed in the substrate between the first portion of the guard region and the first circuit block, wherein the first grounded highly doped region has a third doping concentration of a p-type dopant, and wherein the second doping concentration is higher than the first doping concentration, and the third doping concentration is higher than the second doping concentration.
13. The integrated circuit of claim 12, wherein the first trench has a depth substantially deeper than the p-well block region and the first portion of the guard region.
14. The integrated circuit of claim 12, further comprising:
- a second portion of the guard region formed in the substrate between the p-well block region and the second circuit block, wherein the second portion of the guard region has the second doping concentration.
15. The integrated circuit of claim 14, further comprising:
- a second grounded highly doped region formed in the substrate between the second portion of the guard region and the second circuit block, wherein the second grounded highly doped region has the third doping concentration.
16. The integrated circuit of claim 14, further comprising a second trench formed between the p-well block region and the second portion of the guard region.
17. The integrated circuit of claim 16, wherein the second trench has a depth substantially deeper than the p-well block region and the second portion of the guard region.
18. The integrated circuit of claim 12, wherein the p-well block region is a ring surrounding the first circuit block.
19. The integrated circuit of claim 12, wherein the first portion of the guard region is a ring formed surrounding the first circuit block, between the first circuit block and the p-well block region.
20. The integrated circuit of claim 12, wherein the first grounded highly doped region is a ring formed surrounding the first circuit block, between the first circuit block and the p-well block region.
Type: Application
Filed: Jul 30, 2009
Publication Date: Dec 10, 2009
Applicant: FREESCALE SEMICONDUCTOR, INC. (Austin, TX)
Inventors: Radu M. Secareanu (Phoenix, AZ), Suman K. Banerjee (Chandler, AZ), Olin L. Hartin (Phoenix, AZ)
Application Number: 12/512,616
International Classification: H01L 23/62 (20060101); H01L 23/552 (20060101);