Abstract: System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

Abstract: A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

Abstract: A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

Abstract: System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

Abstract: A multi-layer integrated semiconductor structure is provided, which includes at least a first semiconductor structure and a second semiconductor structure coupled together via an interface. The interface includes at least a first portion adapted to provide a communication interface between the first semiconductor structure and the second semiconductor structure and at least a second portion adapted to reduce electrical interference between the first semiconductor structure and the second semiconductor structure.

Abstract: A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seamless bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

Abstract: A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seam-less bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

Abstract: A multi-layer integrated semiconductor structure is provided, which includes at least a first semiconductor structure and a second semiconductor structure coupled together via an interface. The interface includes at least a first portion adapted to provide a communication interface between the first semiconductor structure and the second semiconductor structure and at least a second portion adapted to reduce electrical interference between the first semiconductor structure and the second semiconductor structure.

Abstract: A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

Abstract: A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seam-less bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

Abstract: A multi-layer integrated semiconductor structure including a first device layer having a first plurality of semiconductor elements. A first insulating layer is disposed over the first device layer and includes at least a first via-hole. A first conductive plug is disposed in the first via-hole. An interface portion is disposed over at least the first conductive plug. The multi-layer integrated semiconductor structure further includes a second device layer. The second device layer includes a second plurality of semiconductor elements disposed on a top surface of a substrate, which includes a second via-hole. A second conductive plug is disposed in the second via-hole. The second device layer is aligned and coupled to the first device layer via the interface portion so that the interface portion provides a communication relationship between the first device layer and the second device layer.

Abstract: The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1-xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1-xGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

Abstract: The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1−xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1−xGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

Abstract: The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1−xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1−xGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

Abstract: The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si.sub.1 -.sub.x Ge.sub.x alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si.sub.1-x Ge.sub.x alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

Abstract: A vertical bipolar transistor is formed along with an IGFET transistor in a process in which the bipolar transistor collector, base and emitter structure is formed in the body of a semiconductor mesa-like structure while the IGFET transistor is formed in and along one of the sidewalls of the structure. Source and drain regions are formed in the structure by ion-implantation using a polysilicon gate electrode formed over a gate insulator on the sidewall as a self-aligning mask.

Abstract: The selective or blanket deposition of titanium silicide using a Very Low Pressure Chemical Vapor Deposition process is described. Silane and titanium tetrachloride are used as the silicon and titanium sources, respectively. A thin polysilicon layer is deposited prior to the silicide deposition to promote the nucleation of titanium silicide. It is shown that selective deposition is possible by controlling the polysilicon and the titanium silicide deposition times. The resulting titanium silicide films have resistivities in the range of 15-25 micro-ohms-cm.

Abstract: A method and apparatus for forming epitaxial thin film layers on substrates having abrupt transitions between layers of different composition or layers of different or like composition with different degrees of doping included therein. Gaseous reactants containing the desired elements to be included in the first film layer are injected into a CVD reaction chamber containing a substrate. The substrate is heated to a temperature high enough to obtain an epitaxial deposit, but low enough so as not to cause decomposition of the reactants. Once the gaseous reactant flows reach steady-state, an electric discharge or plasma is created in the gases to initiate the decomposition reaction and obtain a deposit. In this way, no transient effects are present. Once the deposit has attained sufficient thickness, the electric discharge is turned off to abruptly terminate deposition.

Abstract: This invention relates to a process and apparatus for the Low Pressure Chemical Vapor Deposition (LPCVD) of polycrystalline refractory metal silicides, such as TiSi.sub.2, in a reactor. An oxidized Si wafer is loaded in the reactor. The reactor is pumped down to a pressure of about 10.sup.-7 Torr, or less. The Si substrate is heated to the predetermined deposition temperature of about 630.degree. C. while avoiding heating of the reactor walls. The reactor is then purged with an inert gas, such as nitrogen. Next, polysilicon is deposited on the wafer by introducing SiH.sub.4 into the reactor at a pressure in the order of 0.2 Torr. A layer of polycrystalline titanium silicide is then formed on the polysilicon layer by introducing reactants, such as TiCl.sub.4 and SiH.sub.4, into the reactor at depositon temperatures between about 650.degree. to 700.degree. C. and pressures of between about 50 to 460 m Torr.

Abstract: A method and apparatus for forming epitaxial thin film layers on substrates having abrupt transitions between layers of different composition or layers of different or like composition with different degrees of doping included therein. Gaseous reactants containing the desired elements to be included in the first film layer are injected into a CVD reaction chamber containing a substrate. The substrate is heated to a temperature high enough to obtain an epitaxial deposit, but low enough so as not to cause decomposition of the reactants. Once the gaseous reactant flows reach steady-state, an electric discharge or plasma is created in the gases to initiate the decomposition reaction and obtain a deposit. In this way, no transient effects are present. Once the deposit has attained sufficient thickness, the electric discharge is turned off to abruptly terminate deposition.