Patents by Inventor Raghukiran Sreeramaneni
Raghukiran Sreeramaneni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063788Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.Type: ApplicationFiled: May 2, 2023Publication date: February 22, 2024Applicant: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
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Publication number: 20230403184Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.Type: ApplicationFiled: June 27, 2023Publication date: December 14, 2023Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Patent number: 11689394Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.Type: GrantFiled: April 24, 2020Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Patent number: 11683033Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.Type: GrantFiled: March 7, 2022Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
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Patent number: 11568918Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.Type: GrantFiled: February 8, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
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Publication number: 20220239292Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.Type: ApplicationFiled: March 7, 2022Publication date: July 28, 2022Applicant: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
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Patent number: 11296693Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.Type: GrantFiled: January 27, 2021Date of Patent: April 5, 2022Assignee: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
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Patent number: 11153132Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.Type: GrantFiled: May 19, 2020Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Publication number: 20210158851Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.Type: ApplicationFiled: February 8, 2021Publication date: May 27, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
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Patent number: 10964378Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.Type: GrantFiled: August 22, 2019Date of Patent: March 30, 2021Assignee: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
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Patent number: 10964708Abstract: A device includes a fuse-array mat including a plurality of fuse-array elements. Each fuse-array element includes a fuse comprising a fuse line having less than or equal to 50% of a dimension of the fuse line disposed over an active area of the fuse-array element, wherein the fuse is configured to be activated to indicate a fuse state of the fuse of two possible fuse states of the fuse. Additionally, each fuse-array element includes an access device comprising a gate line having more than 50% of a dimension of the gate line disposed over the active area of the fuse-array element.Type: GrantFiled: June 26, 2018Date of Patent: March 30, 2021Assignee: Micron Technology, Inc.Inventor: Raghukiran Sreeramaneni
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Publication number: 20210057012Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
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Patent number: 10785067Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.Type: GrantFiled: July 30, 2019Date of Patent: September 22, 2020Assignee: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
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Patent number: 10783937Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.Type: GrantFiled: December 20, 2019Date of Patent: September 22, 2020Assignee: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, Jennifer E. Taylor
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Publication number: 20200280467Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Publication number: 20200252244Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.Type: ApplicationFiled: April 24, 2020Publication date: August 6, 2020Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Patent number: 10666470Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.Type: GrantFiled: February 28, 2019Date of Patent: May 26, 2020Assignee: Micron Technology, Inc.Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Patent number: 10644909Abstract: A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.Type: GrantFiled: May 29, 2019Date of Patent: May 5, 2020Assignee: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, Jennifer E. Taylor
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Patent number: 10637692Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.Type: GrantFiled: September 26, 2017Date of Patent: April 28, 2020Assignee: Micron Technology, Inc.Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Publication number: 20200126602Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Inventors: Raghukiran Sreeramaneni, Jennifer E. Taylor