Patents by Inventor Raghukiran Sreeramaneni
Raghukiran Sreeramaneni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190147968Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.Type: ApplicationFiled: December 11, 2018Publication date: May 16, 2019Inventors: Raghukiran Sreeramaneni, William J. Wilcox, Girish N. Cherussery
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Patent number: 10291439Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.Type: GrantFiled: December 13, 2017Date of Patent: May 14, 2019Assignee: Micron Technology, Inc.Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Publication number: 20190097846Abstract: A device includes one or more memory banks configured to store data. The device also includes a data receiver configured to receive distorted input data as part of a data stream, apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, and generate the data by applying the correction factor to the distorted data. The device further includes a test circuit internal to the device, wherein the test circuit is configured to generate the data stream.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Raghukiran Sreeramaneni, Jennifer E. Taylor, Liang Liu
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Publication number: 20190096445Abstract: A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled to the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.Type: ApplicationFiled: November 29, 2018Publication date: March 28, 2019Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Publication number: 20190097848Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Patent number: 10236072Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.Type: GrantFiled: June 28, 2018Date of Patent: March 19, 2019Assignee: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, William J. Wilcox, Girish N. Cherussery
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Patent number: 10218340Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.Type: GrantFiled: December 22, 2017Date of Patent: February 26, 2019Assignee: Micron Technology, Inc.Inventors: Hideyuki Ichida, Raghukiran Sreeramaneni
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Patent number: 10153922Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.Type: GrantFiled: January 16, 2018Date of Patent: December 11, 2018Assignee: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
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Patent number: 10147466Abstract: A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled o the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.Type: GrantFiled: September 26, 2017Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
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Patent number: 10115474Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.Type: GrantFiled: November 16, 2017Date of Patent: October 30, 2018Assignee: Micron Technology, Inc.Inventors: Raghukiran Sreeramaneni, William J. Wilcox, Girish N. Cherussery
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Publication number: 20180123573Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.Type: ApplicationFiled: December 22, 2017Publication date: May 3, 2018Applicant: Micron Technology, Inc.Inventors: Hideyuki Ichida, Raghukiran Sreeramaneni
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Patent number: 9941870Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.Type: GrantFiled: September 9, 2015Date of Patent: April 10, 2018Assignee: Micron Technology, Inc.Inventors: Hideyuki Ichida, Raghukiran Sreeramaneni
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Publication number: 20170070219Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.Type: ApplicationFiled: September 9, 2015Publication date: March 9, 2017Inventors: HIDEYUKI ICHIDA, RAGHUKIRAN SREERAMANENI
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Patent number: 9213553Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.Type: GrantFiled: October 4, 2013Date of Patent: December 15, 2015Assignee: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni, Suryanarayana B. Tatapudi
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Publication number: 20140040922Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.Type: ApplicationFiled: October 4, 2013Publication date: February 6, 2014Applicant: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni, Suryanarayana B. Tatapudi
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Patent number: 8566846Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.Type: GrantFiled: April 4, 2008Date of Patent: October 22, 2013Assignee: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni, Suryanarayana B. Tatapudi
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Patent number: 7804324Abstract: Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device coupled to each other in parallel; a second plurality of switching devices coupled to each other in parallel and coupled in series with the reference circuit between a supply node and a supply return node; and processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance of the reference circuit than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices.Type: GrantFiled: August 11, 2009Date of Patent: September 28, 2010Assignee: Micron Technology, Inc.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
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Patent number: 7755385Abstract: A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed such that when a leg is not being utilized, the tuning transistors in the unused leg are placed in a tri-state. For example, during an ODT mode of the output driver, the tuning transistors in the non-ODT legs are tri-stated. During a READ mode of the output driver, the tuning transistors in the ODT legs are tri-stated. During a HiZ mode of the output driver, the tuning transistors in both legs are tri-stated. Tri-stating the tuning transistors in the unused output driver legs can reduce DQ pin capacitance by a total of approximately (Cgd+Cgs+Cgb).Type: GrantFiled: December 22, 2008Date of Patent: July 13, 2010Assignee: Micron Technology, Inc.Inventor: Raghukiran Sreeramaneni
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Publication number: 20090295426Abstract: Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device coupled to each other in parallel; a second plurality of switching devices coupled to each other in parallel and coupled in series with the reference circuit between a supply node and a supply return node; and processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance of the reference circuit than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices.Type: ApplicationFiled: August 11, 2009Publication date: December 3, 2009Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
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Publication number: 20090254925Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.Type: ApplicationFiled: April 4, 2008Publication date: October 8, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni, Suryanarayana B. Tatapudi