Patents by Inventor Raghuveer R. Patlolla

Raghuveer R. Patlolla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148296
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 16, 2019
    Inventors: Benjamin D. Briggs, Elbert E. Huang, RAGHUVEER R. PATLOLLA, CORNELIUS BROWN PEETHALA, DAVID L. RATH, CHIH-CHAO YANG
  • Patent number: 10242872
    Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Prasad Bhosale, Donald F. Canaperi, Raghuveer R. Patlolla, Cornelius B. Peethala, Hosadurga Shobha, Theodorus E. Standaert
  • Patent number: 10211153
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath, Chih-Chao Yang
  • Patent number: 10204829
    Abstract: Methods for fabricating low-resistivity metallic interconnect structures with self-forming diffusion barrier layers are provided, as well as semiconductor devices comprising low-resistivity metallic interconnect structures with self-formed diffusion barrier layers. For example, a semiconductor device includes a dielectric layer disposed on a substrate, an opening etched in the dielectric layer, a metallic liner layer covering sidewall and bottom surfaces of the opening in the dielectric layer, copper material filling the opening to form an interconnect structure, and a self-formed diffusion barrier layer formed in the sidewall surfaces of the opening of the dielectric layer. The self-formed diffusion barrier layer includes manganese atoms which are diffused into the sidewall surfaces of the dielectric layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hari P. Amanapu, Cornelius Brown Peethala, Raghuveer R. Patlolla, Chih-Chao Yang, Takeshi Nogami
  • Patent number: 10177030
    Abstract: Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to annealing after which the stress control layer can be removed. The stress control layer prevents formation of defects that can occur in the absence of the stress control layer.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari P. Amanapu, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Publication number: 20180358230
    Abstract: A method is presented for post chemical mechanical polishing (PCMP) clean for cleaning a chemically-mechanically polished semiconductor wafer. The method includes planarizing the semiconductor wafer, subjecting the semiconductor wafer to a de-oxygenated mixture of DI water and PCMP solution, and applying a de-oxygenated environment during the cleaning. The solution can be de-oxygenated by nitrogen degas or by introducing a reducing agent. The environment can be de-oxygenated by purging with an inert gas, such as nitrogen.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventors: Donald F. Canaperi, Pavan S. Chinthamanipeta, Raghuveer R. Patlolla, Cornelius B. Peethala
  • Publication number: 20180358231
    Abstract: A method is presented for post chemical mechanical polishing (PCMP) clean for cleaning a chemically-mechanically polished semiconductor wafer. The method includes planarizing the semiconductor wafer, subjecting the semiconductor wafer to a de-oxygenated mixture of DI water and PCMP solution, and applying a de-oxygenated environment during the cleaning. The solution can be de-oxygenated by nitrogen degas or by introducing a reducing agent. The environment can be de-oxygenated by purging with an inert gas, such as nitrogen.
    Type: Application
    Filed: December 4, 2017
    Publication date: December 13, 2018
    Inventors: Donald F. Canaperi, Pavan S. Chinthamanipeta, Raghuveer R. Patlolla, Cornelius B. Peethala
  • Patent number: 10096769
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180287051
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Application
    Filed: June 5, 2018
    Publication date: October 4, 2018
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180277369
    Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 27, 2018
    Inventors: John C. Arnold, Prasad Bhosale, Donald F. Canaperi, Raghuveer R. Patlolla, Cornelius B. Peethala, Hosadurga Shobha, Theodorus E. Standaert
  • Publication number: 20180261759
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 13, 2018
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180197774
    Abstract: Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to annealing after which the stress control layer can be removed. The stress control layer prevents formation of defects that can occur in the absence of the stress control layer.
    Type: Application
    Filed: November 2, 2017
    Publication date: July 12, 2018
    Inventors: Hari P. Amanapu, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Publication number: 20180197773
    Abstract: Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to annealing after which the stress control layer can be removed. The stress control layer prevents formation of defects that can occur in the absence of the stress control layer.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 12, 2018
    Inventors: Hari P. Amanapu, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Patent number: 10002831
    Abstract: A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer, conformally depositing a barrier layer on the dielectric layer and on sides and a bottom of each one of the plurality of openings, depositing a contact layer on the barrier layer in each one of the plurality of openings, removing a portion of each contact layer from each one of the plurality of openings, and removing a portion of the barrier layer from each one of the plurality of openings, wherein at least the removal of the portion of the barrier layer is performed using an etchant including: (a) a compound selected from group consisting of -azole, -triazole, and combinations thereof; (b) a compound containing one or more peroxy groups; (c) one or more alkaline metal hydroxides; and (d) water.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Raghuveer R. Patlolla, Cornelius B. Peethala, David L. Rath, Hosadurga Shobha
  • Publication number: 20180114718
    Abstract: A method for forming interconnect structures includes forming a barrier material over a dielectric layer having a trench, the barrier layer being disposed on sidewalls and horizontal surfaces of the trench, depositing an interconnect layer over the barrier layer to form an interconnect structure, recessing the interconnect layer down to a surface of the barrier layer using a chemical mechanical planarization process, and planarizing the barrier layer and the interconnect layer using a wet etch process to form a coplanar surface to prevent dishing or divots in the interconnect structure.
    Type: Application
    Filed: March 20, 2017
    Publication date: April 26, 2018
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Takeshi Nogami, Raghuveer R. Patlolla, Cornelius B. Peethala, David L. Rath
  • Publication number: 20180114719
    Abstract: A method for forming interconnect structures includes forming a barrier material over a dielectric layer having a trench, the barrier layer being disposed on sidewalls and horizontal surfaces of the trench, depositing an interconnect layer over the barrier layer to form an interconnect structure, recessing the interconnect layer down to a surface of the barrier layer using a chemical mechanical planarization process, and planarizing the barrier layer and the interconnect layer using a wet etch process to form a coplanar surface to prevent dishing or divots in the interconnect structure.
    Type: Application
    Filed: November 27, 2017
    Publication date: April 26, 2018
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Takeshi Nogami, Raghuveer R. Patlolla, Cornelius B. Peethala, David L. Rath
  • Patent number: 9934980
    Abstract: A method utilizing a chemical mechanical polishing process to remove a patterned material stack comprising at least one pattern transfer layer and a template layer during a rework process or during a post pattern transfer cleaning process is provided. The pattern in the patterned material stack is formed by pattern transfer of a directed self-assembly pattern generated from microphase separation of a self-assembly material.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jassem A. Abdallah, Raghuveer R. Patlolla, Brown C. Peethala
  • Publication number: 20180082955
    Abstract: Semiconductor structures including copper interconnect structures and methods include selective surface modification of copper by providing a CuxTiyNz alloy in the surface. The methods generally include forming a titanium nitride layer on an exposed copper surface followed by annealing to form the CuxTiyNz, alloy in the exposed copper surface. Subsequently, the titanium layer is removed by a selective wet etching.
    Type: Application
    Filed: October 4, 2017
    Publication date: March 22, 2018
    Inventors: Raghuveer R. Patlolla, Cornelius Brown Peethala, Roger A. Quon, Chih-Chao Yang
  • Publication number: 20180061761
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Benjamin D. Briggs, Elbert E. Huang, RAGHUVEER R. PATLOLLA, CORNELIUS BROWN PEETHALA, DAVID L. RATH, CHIH-CHAO YANG
  • Patent number: 9881833
    Abstract: A method for forming interconnect structures includes forming a barrier material over a dielectric layer having a trench, the barrier layer being disposed on sidewalls and horizontal surfaces of the trench, depositing an interconnect layer over the barrier layer to form an interconnect structure, recessing the interconnect layer down to a surface of the barrier layer using a chemical mechanical planarization process, and planarizing the barrier layer and the interconnect layer using a wet etch process to form a coplanar surface to prevent dishing or divots in the interconnect structure.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Takeshi Nogami, Raghuveer R. Patlolla, Cornelius B. Peethala, David L. Rath