Patents by Inventor Raghuveer R. Patlolla
Raghuveer R. Patlolla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11804378Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.Type: GrantFiled: December 31, 2021Date of Patent: October 31, 2023Assignee: International Business Machines CorporationInventors: Raghuveer R Patlolla, Donald F Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton
-
Publication number: 20230215734Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.Type: ApplicationFiled: December 31, 2021Publication date: July 6, 2023Inventors: Raghuveer R. Patlolla, Donald F. Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton
-
Patent number: 11205587Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.Type: GrantFiled: November 15, 2019Date of Patent: December 21, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Su Chen Fan, Hemanth Jagannathan, Raghuveer R. Patlolla, Cornelius Brown Peethala
-
Patent number: 11094527Abstract: A method for implementing a wet clean process includes cleaning one or more trenches formed in an interlevel dielectric by applying a two-phase cleaning solution. Applying the two-phase cleaning solution includes applying a first component of the two-phase cleaning solution including a diluted acid solution, and reducing capillary force during drying by applying a second component of the two-phase cleaning solution including a chemistry that is less dense than the first component.Type: GrantFiled: October 10, 2018Date of Patent: August 17, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cornelius B. Peethala, Chih-Chao Yang, Raghuveer R. Patlolla, Hsueh-Chung Chen
-
Patent number: 11037875Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.Type: GrantFiled: March 26, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
-
Patent number: 11031339Abstract: Interconnect structures and processes of fabricating the interconnect structures generally includes a recessed metal conductor and a discontinuous capping layer thereon. The discontinuous “capped” metal interconnect structure provides improved performance and reliability for the semiconductor industry.Type: GrantFiled: November 19, 2019Date of Patent: June 8, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
-
Patent number: 11031250Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.Type: GrantFiled: November 29, 2018Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Mona A. Ebrish, Michael Rizzolo, Son Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi
-
Patent number: 11031337Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.Type: GrantFiled: June 19, 2019Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
-
Patent number: 11018087Abstract: Interconnect structures and processes of fabricating the interconnect structures generally includes a recessed metal conductor and a discontinuous capping layer thereon. The discontinuous “capped” metal interconnect structure provides improved performance and reliability for the semiconductor industry.Type: GrantFiled: April 25, 2018Date of Patent: May 25, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
-
Publication number: 20210043563Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.Type: ApplicationFiled: October 12, 2020Publication date: February 11, 2021Inventors: Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla
-
Patent number: 10910307Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include one or more metal filled via structures within a dielectric layer of an interconnect level, wherein at least one of the metal filled via structures includes a bulk metal and a metal alloy overlaying the bulk metal, wherein the bulk metal and metal alloy filled via is coupled to an active circuit.Type: GrantFiled: November 2, 2018Date of Patent: February 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raghuveer R. Patlolla, James J. Kelly, Cornelius Brown Peethala, Chih-Chao Yang
-
Patent number: 10903161Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include one or more metal filled via structures within a dielectric layer of an interconnect level, wherein at least one of the metal filled via structures includes a bulk metal and a metal alloy overlaying the bulk metal, wherein the bulk metal and metal alloy filled via is coupled to an active circuit.Type: GrantFiled: November 13, 2019Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raghuveer R. Patlolla, James J. Kelly, Cornelius Brown Peethala, Chih-Chao Yang
-
Patent number: 10832917Abstract: A method is presented for post chemical mechanical polishing (PCMP) clean for cleaning a chemically-mechanically polished semiconductor wafer. The method includes planarizing the semiconductor wafer, subjecting the semiconductor wafer to a de-oxygenated mixture of DI water and PCMP solution, and applying a de-oxygenated environment during the cleaning. The solution can be de-oxygenated by nitrogen degas or by introducing a reducing agent. The environment can be de-oxygenated by purging with an inert gas, such as nitrogen.Type: GrantFiled: June 9, 2017Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Pavan S. Chinthamanipeta, Raghuveer R. Patlolla, Cornelius B. Peethala
-
Publication number: 20200328156Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.Type: ApplicationFiled: May 29, 2020Publication date: October 15, 2020Inventors: Benjamin D. Briggs, Elbert Huang, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath, Chih-Chao Yang
-
Patent number: 10804193Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.Type: GrantFiled: May 31, 2017Date of Patent: October 13, 2020Assignee: Tessera, Inc.Inventors: Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla
-
Patent number: 10741748Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.Type: GrantFiled: June 25, 2018Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph F. Maniscalco, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
-
Publication number: 20200219759Abstract: A semiconductor device includes one or more interconnects and one or more cap layers disposed on respective ones of the one or more interconnects. The one or more cap layers include a material that has properties permitting selective deposition on the one or more interconnects.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: Cornelius B. Peethala, Raghuveer R. Patlolla, Chih-Chao Yang, Roger A. Quon
-
Patent number: 10699945Abstract: A method for back end of line (BEOL) integration for one or more interconnects includes forming one or more interconnects by depositing conductive material on a diffusion barrier layer in respective ones of one or more trenches formed within an interlevel dielectric, forming one or more cap layers on respective ones of the one or more interconnects, and selectively etching the diffusion barrier relative to the one or more cap layers to remove portions of the diffusion barrier layer along the interlevel dielectric.Type: GrantFiled: October 4, 2018Date of Patent: June 30, 2020Assignee: International Business Machines CorporationInventors: Cornelius B. Peethala, Raghuveer R. Patlolla, Chih-Chao Yang, Roger A. Quon
-
Patent number: 10685876Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.Type: GrantFiled: September 18, 2018Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Su Chen Fan, Hemanth Jagannathan, Raghuveer R. Patlolla, Cornelius Brown Peethala
-
Patent number: 10686126Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.Type: GrantFiled: November 13, 2019Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINESS CORPORATIONInventors: Joseph F. Maniscalco, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang