Abstract: A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality of BIST memory ports are used to generate multiple memory test instructions in parallel, and the parallel instructions are then merged to generate a single memory test instruction stream at a speed that is a multiple of the BIST operating frequency.

Abstract: This invention permits user controlled cache coherence operations with the flexibility to do these operations on all levels of cache together or each level independently. In the case of an all level operation, the user does not have to monitor and sequence each phase of the operation. This invention also provides a way for users to track completion of these operations. This is critical for multi-core/multi-processor devices. Multiple cores may be accessing the end point and the user/application needs to be able to identify when the operation from one core is complete, before permitting other cores access that data or code.

Abstract: In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored.

Abstract: In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file.

Abstract: A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.

Abstract: A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed.

Abstract: This invention is a data processing system including a central processing unit, an external interface, a level one cache, level two memory including level two unified cache and directly addressable memory. A level two memory controller includes a directly addressable memory read pipeline, a central processing unit write pipeline, an external cacheable pipeline and an external non-cacheable pipeline.

Abstract: A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream.

Abstract: This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be trated as a cache miss to ensure that the requesting CPU will receive valid data.

Abstract: A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.

Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd.

Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

Abstract: A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality of BIST memory ports are used to generate multiple memory test instructions in parallel, and the parallel instructions are then merged to generate a single memory test instruction stream at a speed that is a multiple of the BIST operating frequency.

Abstract: This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.