Abstract: This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used in test in native form or in inverted form. Different built-in self test instructions update pointer including reset to the first bit, no change, increment to the next bit and decrement to the previous bit. For write instructions the selected normal or inverted data is written into memory. For read instructions the selected normal or inverted data is compared with data read from a memory.

Abstract: Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made programmable and subject to adjustment as part of wafer probe testing. The techniques of parametric adjustment presented are based upon what is commonly referred to as clock skewing or clock tuning. The invention describes methods to select the clock skewing on a die-to-die basis based on functional testing with the actual parametric limits imposed on parameters of interest. The results associated with each die form the basis for hard-programming the selected clock skew value into the die via electrical fuses.

Abstract: Instead of using point to point connections between the memory and the memory test controller, a unique address is assigned to each memory element. The memory elements and the single memory test controller are interconnected by a hierarchal datapath both for the memory addresses and for the resultant data being returned to the memory test controller.

Abstract: A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.

Abstract: In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.

Abstract: The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.

Abstract: A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.

Abstract: Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made programmable and subject to adjustment as part of wafer probe testing. The techniques of parametric adjustment presented are based upon what is commonly referred to as clock skewing or clock tuning. The invention describes methods to select the clock skewing on a die-to-die basis based on functional testing with the actual parametric limits imposed on parameters of interest. The results associated with each die form the basis for hard-programming the selected clock skew value into the die via electrical fuses.

Abstract: An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory access processor hub is a second module, known as the hub interface unit hub interface unit which serves several functions. It provides buffering for read and write data, it prioritizes read and write commands from the source and destination pipelines such that the port sees a single interface with both access types consolidated and finally, it acts to decouple the port interface clock domain from the core processor clock domain through synchronization.

Abstract: In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.