Abstract: An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.

Abstract: A method and apparatus for dynamically arbitrating, in hardware, requests for a resource shared among multiple clients. Multiple data streams or service requests require access to a shared resource, such as memory, communication bandwidth, etc. A hardware arbiter monitors the streams' traffic levels and determines when one or more of their arbitration weights should be adjusted. When a queue used by one of the streams is filled to a threshold level, the hardware reacts by quickly and dynamically modifying that queue's arbitration weight. Therefore, as the queue is filled or emptied to different thresholds, the queue's arbitration weight rapidly changes to accommodate the corresponding client's temporal behavior. The arbiter may also consider other factors, such as the client's type of traffic, a desired quality of service, available credits, available descriptors, etc.

Abstract: A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.

Abstract: A universal DMA (Direct Memory Access) engine can be dynamically configured to function in either a receive or transmit mode. DMAs are logically assembled and bound as needed, without limitation to a fixed, pre-determined number of receive engines and transmit engines. Because a DMA engine may be dynamically assembled to support the flow of data in either direction, varied usage models are enabled, and components used to assemble a receive DMA engine for one application may be subsequently used to assemble a transmit engine for a different application. An application may request a specific number of each type of engine, depending on the nature of its input/output traffic. The number of receive or transmit engines can be dynamically increased or decreased without suspending or rebooting the host. A universal DMA architecture provides a unified software framework, thereby decreasing the complexity of the software and the hardware gate count cost.

Abstract: A system and method for validating packet classification within an input/output device or component. Based on a target DMA engine within the device, and a protocol path for testing the DMA engine, sets of packet attributes are generated and used to format packets for input to the device. The output of the device is examined to determine if the correct DMA engine was used within the device. The DMA policy specifying which DMA engine to use for a particular packet configuration or set of protocol attributes can be dynamically replaced or modified without halting the validation process.

Abstract: A reorder mechanism for use with a relaxed order interconnect device. The reorder mechanism includes a buffer module and a reorder module coupled to the buffer module is disclosed. The reorder module enables movement of multiple packets between a plurality of resources. The movement of multiple packets of information has a relaxed ordering of data transfers associated with multiple packets and also a relaxed ordering of data transfers associated with any single packet.

Abstract: A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in a verification layer that employs multiple queues to simulate receipt of input data, submission to an output port and transmission from the device. Call backs are employed to signal completion of events related to receipt of data at the device and modeling of data processing within the verification layer. As call backs are resolved, corresponding tasks are executed to advance the processing of the data through the verification layer. A device-specific algorithm is executed in the verification layer to predict the ordering of output from the device, and that output is compared to the predicted output by a transmission checker.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: An interface is provided to couple an input/output device (e.g., a network interface unit) to one or more different host system buses without altering the configuration of the device (e.g., to include logic specific to the host buses). Functionality of the device (e.g., MTU size, error detection) is therefore independent of the host bus. Host bus logic for managing operation of the host bus is augmented with logic for translating between semantics of the interface and the host bus. Also, end-to-end verification of a complex ASIC in multiple configurations or environments can be performed over the interface without probing into the ASIC.

Abstract: Systems and related methods are described for handling one or more resource requests. A protocol engine receives a resource request in accordance with a prescribed protocol, and a classification engine determines a desired class of service for the request. An analysis engine optionally analyzes the request, and, responsive thereto, determines a desired sub-class of service for the request. A policy engine then allocates a resource to the request responsive to one or both of the desired class of service, and the desired sub-class of service.

Abstract: A method and apparatus for dynamically arbitrating, in hardware, requests for a resource shared among multiple clients. Multiple data streams or service requests require access to a shared resource, such as memory, communication bandwidth, etc. A hardware arbiter monitors the streams' traffic levels and determines when one or more of their arbitration weights should be adjusted. When a queue used by one of the streams is filled to a threshold level, the hardware reacts by quickly and dynamically modifying that queue's arbitration weight. Therefore, as the queue is filled or emptied to different thresholds, the queue's arbitration weight rapidly changes to accommodate the corresponding client's temporal behavior. The arbiter may also consider other factors, such as the client's type of traffic, a desired quality of service, available credits, available descriptors, etc.

Abstract: A method for maximizing page locality within a networking system operationally attached to a plurality of processing entities wherein each processing entity either shares or includes a corresponding memory hierarchy wherein each memory hierarchy has a table of pages temporally managed by access from the networking system is disclosed. The method includes providing at least one memory access channel to each memory hierarchy and moving information to and from pages in the memory hierarchy of a particular processing entity via its associated memory access channels.

Abstract: A packet reassembly system includes a buffer for storing information elements included in one or more incoming packets, a memory for storing validity indicators corresponding to the information elements, a first logic circuit capable of setting the validity indicators based on the information elements stored in the buffer, and a second logic circuit capable of determining the contiguity of the information elements stored in the buffer based on the settings of the validity indicators.

Abstract: A network switch architected using multiple processor engines includes a method and system for ensuring temporal consistency of data and resources as packet traffic flows through the switch. Upon receiving a connection request, the switch internally associates a semaphore with the connection. The semaphore is distributed and stored at the processing engines. Each of the processing engines performs specific operations relating to incoming packets associated with the connection. Internal messages are passed between the processing engines to coordinate and control these operations. Some of these messages can include a semaphore value. Upon receiving such a message, a processing engine compares the semaphore value to a stored semaphore. Packets relating to the connection identified by the message are processed if there is a match between the semaphores. Also, the semaphore value can be moved from one processing engine to another in order to control the allocation and de-allocation of resources.

Abstract: A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.

Abstract: A network system which provides asymmetrical processing for networking functions and data path offload. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions.

Abstract: A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.

Abstract: A network switch includes a first content addressable memory (CAM), a second CAM, a binding lookup table (BLT), and a packet manager. The BLT extracts two sets of header information from ingressing packets. The first set is applied the first CAM to retrieve a service policy index. The second set of header information is applied to the second CAM to determine whether a connection already exists. If a connection exists, a flow transmission control block (fTCB) pointer is retrieved from the second CAM. Otherwise, if there is no current connection for the packet, a check is made of the service policy index to determine the level of service associated with the packet. Based on the assigned service level, a new fTCB pointer is retrieved, or alternatively, client and server TCB pointers are retrieved. The packet manager then processes the packet according to which TCB pointer is retrieved.

Abstract: A method for the loading and unloading of a FIFO in an isochronous transmission mechanism uses descriptor blocks which have both branch addresses and skip addresses. The method can recover from cycle loss by selectively resending or skipping a packet that should have been sent in the lost cycle. The method also works two cycles ahead of schedule, in an attempt to keep the FIFO loaded with all of the packets for two cycles of transmission. The FIFO is filled according to a DMA algorithm and drained according to a Link algorithm where the two algorithms are coordinated to communicate information about lost cycles and current demands or opportunities for transmission. If the Link algorithm detects a lost cycle, it communicates that to the DMA algorithm and the DMA algorithm seeks to compensate appropriately. These two algorithms describe mechanisms for the DMA and Link sides of an isochronous transmitter.