Patents by Inventor Rahul Jairath

Rahul Jairath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5688360
    Abstract: A semiconductor wafer polishing apparatus includes a housing and a turntable mounted in the housing. The turntable has an axis of rotation and a surface for affixing a semiconductor wafer. The polishing apparatus also includes a motor mounted to the housing and connected to the turntable to supply a torque for rotating the turntable about the axis of rotation. A polishing assembly is connected to the housing and extends adjacent to the turntable surface. A polishing pad is affixed to the polishing assembly and is positionable to contact the semiconductor wafer. Some polishing pads are cylindrical in form. Other polishing pads have a conical form.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: November 18, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Rahul Jairath
  • Patent number: 5665656
    Abstract: A semiconductor wafer polishing apparatus includes a housing and a turntable mounted in the housing. The turntable has an axis of rotation and a surface for affixing a semiconductor wafer. The polishing apparatus also includes a motor mounted to the housing and connected to the turntable to supply a torque for rotating the turntable about the axis of rotation. A polishing assembly is connected to the housing and extends adjacent to the turntable surface. A polishing pad is affixed to the polishing assembly and is positionable to contact the semiconductor wafer. Some polishing pads are cylindrical in form. Other polishing pads have a conical form.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: September 9, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Rahul Jairath
  • Patent number: 5614444
    Abstract: A method of using additives with silica-based slurries to enhance metal selectivity in polishing metallic materials utilizing a chemical-mechanical polishing (CMP) process. Additives are used with silica-based slurries to passivate a dielectric surface, such as a silicon dioxide (SiO.sub.2) surface, of a semiconductor wafer so that dielectric removal rate is reduced when CMP is applied. The additive is comprised of at least a polar component and an apolar component. The additive interacts with the surface silanol group of the SiO.sub.2 surface to inhibit particles of the silica-based slurry from interacting with hydroxyl molecules of the surface silanol group. By applying a surface passivation layer on the SiO.sub.2 surface, erosion of the SiO.sub.2 surface is reduced. However, the metallic surface is not influenced significantly by the additive, so that the selectivity of metal removal over oxide removal is enhanced.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 25, 1997
    Assignees: Sematech, Inc., Intel Corporation, National Semiconductor Corp., Digital Equipment Corp.
    Inventors: Janos Farkas, Rahul Jairath, Matt Stell, Sing-Mo Tzeng
  • Patent number: 5478435
    Abstract: A point of use slurry dispensing system with controls for dilution, temperature and oxidizer/etchant/additive infusion. A slurry in unmixed form and a diluting agent are independently pumped to a pad on a CMP tool. Liquid heaters are used to heat the slurry and the diluting agent to a desirable temperature. The actual mixing occurs at the point of use on the pad or in a dispensing line just prior to the point of use. In some instances a third independent distribution line is used to dispense an oxidizer, etchant and/or chemical additive at or near the point of use.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: December 26, 1995
    Assignees: National Semiconductor Corp., Sematech Inc., AT&T GIS
    Inventors: James J. Murphy, Janos Farkas, Lucia C. Markert, Rahul Jairath