Abstract: Improved reliability, availability, and serviceability (RAS) is provided by an extensible and flexible firmware architecture. The architecture provides management for events, where an event is a response to an imminent failure of or capacity change requirement applicable to a component of the system. In response to an event, control of a system is transferred from an operating system to the firmware manager. The manager identifies an action that is specified by the event. Based on the action, the firmware manager selects a firmware handler from a plurality of firmware handlers. The firmware manager dispatches the selected firmware handler to perform the specified action. The firmware manager and the dispatched firmware handler exchange system-independent information regarding the event. The firmware manager also manages time-slices for the performance of the specified action by the dispatched firmware handler.

Abstract: Methods and apparatus to simplify configuration calculation and management of a processor system are disclosed. An example disclosed method reads system configuration data from registers of a processing system, caches the system configuration data in an allocated memory, and calculates new system configuration data for the processing system by operating on cached data. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a resource power controller. In some embodiments, an integrated circuit includes a resource power controller to control whether a resource is in an up state or a down state. In some embodiments, the resource power controller heuristically estimates when to return the resource to an up state based, at least in part, on an estimate of a gap size.

Abstract: In one embodiment, the present invention includes a method for dynamically discovering a topology of a system having a plurality of point-to-point (PTP) links via a routine that communicates a link exchanged parameter with at least one component coupled to a system bootstrap processor (SBSP), sets a minimal set of routing infrastructure information based on the communication, and determines presence of a neighboring component to a target component based on a communication from the SBSP to the target component using the minimal set of routing infrastructure information. Other embodiments are described and claimed.

Abstract: Machine-readable media, methods, apparatus and system for caption detection are described. In some embodiments, during a non-quiesce state of a system, a configuration data for a configuration update of a configurable device of the system may be calculated, and it may be determined whether the configuration data is final configuration data or intermediate configuration data, wherein the final configuration data may be used to directly enact the configuration update during a quiesce state of the system, while the intermediate configuration data is used to indirectly enact the configuration update during the quiesce state of the system. Further, during the non-quiesce state of the system, if the configuration data is the intermediate configuration data, then codes associated with the configuration data may be determined, wherein the codes may be used to operate the configuration data to obtain the final configuration data during the quiesce state of the system.

Abstract: Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for enabling an integrated memory controller to transparently work with defective memory devices. In some embodiments, a marginal condition is imposed on a memory module during normal operations of the memory module. The term “marginal condition” refers to a condition that is out of compliance with a specified (or “normal”) operating condition for the memory module. The memory module may exhibit failures in response to the marginal conditions and compensating mechanisms may mitigate the failures.

Abstract: In some embodiments, a memory control device includes a sensor positioned remotely from a memory device, a register to store an offset value, the offset value corresponding to a difference between a temperature reading of the sensor and an estimated actual temperature of the memory device, and a controller to control an operation of the memory device, wherein the controller is configured to read the offset value from the register and control the operation of the memory device in accordance with the offset value. The controller may be configured to dynamically update the offset value during an operation of the memory device. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatus to change a configuration of a processor system are disclosed. An example disclosed method calculates system configuration data during a non-quiesce state of a processing system, stores information based on the calculated system configuration data in a data buffer during the non-quiesce state of the processing system, and extracts information from the data buffer to update the configuration of the processing system while the processing system is in a quiesce state.

Abstract: Methods and systems for performing network port authentication without requiring any operating system (OS) complicity are disclosed. Under one method, port authentication instructions are loaded into a protected memory space during a pre-boot of a supplicant system. In response to a port authentication request, the supplicant system's processor is switched to a hidden execution mode and executes the port authentication instructions to authenticate a network port hosted by an authenticator system to which the supplicant system is linked. One authentication process employs an authentication server that authenticates the supplicant via one of various authentication schemes, including an access challenge. Port authentication may also be performed via an out-of-band base management controller that operates independently from an operating system running on the supplicant.

Abstract: Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.

Abstract: Methods and apparatus to simplify configuration calculation and management of a processor system are disclosed. An example disclosed method reads system configuration data from registers of a processing system, caches the system configuration data in an allocated memory, and calculates new system configuration data for the processing system by operating on cached data. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, the present invention includes a method for dynamically discovering a topology of a system having a plurality of point-to-point (PTP) links via a routine that communicates a link exchanged parameter with at least one component coupled to a system bootstrap processor (SBSP), sets a minimal set of routing infrastructure information based on the communication, and determines presence of a neighboring component to a target component based on a communication from the SBSP to the target component using the minimal set of routing infrastructure information. Other embodiments are described and claimed.

Abstract: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for local and remote access to a resource. In some embodiments, an integrated circuit includes a configurable hardware resource. In addition, the integrated circuit may also include access control logic to authenticate agents that attempt to configure the resource. In some embodiments, the agents may be in-band or out-of-band agents. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a resource power controller. In some embodiments, an integrated circuit includes a resource power controller to control whether a resource is in an up state or a down state. In some embodiments, the resource power controller heuristically estimates when to return the resource to an up state based, at least in part, on an estimate of a gap size.

Abstract: A technique for providing communication between two computers through a network in a way to allow one computer to control the other.

Abstract: Methods and apparatus to change a configuration of a processor system are disclosed. An example disclosed method calculates system configuration data during a non-quiesce state of a processing system, stores information based on the calculated system configuration data in a data buffer during the non-quiesce state of the processing system, and extracts information from the data buffer to update the configuration of the processing system while the processing system is in a quiesce state.

Abstract: Improved reliability, availability, and serviceability (RAS) is provided by an extensible and flexible firmware architecture. The architecture provides management for events, where an event is a response to an imminent failure of or capacity change requirement applicable to a component of the system. In response to an event, control of a system is transferred from an operating system to the firmware manager. The manager identifies an action that is specified by the event. Based on the action, the firmware manager selects a firmware handler from a plurality of firmware handlers. The firmware manager dispatches the selected firmware handler to perform the specified action. The firmware manager and the dispatched firmware handler exchange system-independent information regarding the event. The firmware manager also manages time-slices for the performance of the specified action by the dispatched firmware handler.

Abstract: Methods and apparatus to provide dual-mode drivers in a processor system are disclosed. An example method disclosed herein comprises including operating system (OS) agnostic mode services that are available during an OS agnostic mode to allow a single set of drivers to be used during boot mode and the OS agnostic mode. The example method further comprises including a dual-mode library that is capable of determining the current operating mode of the processor system and binding the drivers to available services accordingly.