Patents by Inventor Rahul Mathur
Rahul Mathur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250259671Abstract: A read circuitry for memory includes a column read-out multiplexer (MUX) coupled to a set of columns of the memory, wherein the column read-out MUX receives a column select signal from a control circuit to output a corresponding column output from the set of columns; and a single sense amplifier coupled to receive the corresponding column output of the column read-out MUX.Type: ApplicationFiled: February 8, 2024Publication date: August 14, 2025Inventors: Akshay Kumar, Edward Martin McCombs, JR., Rahul Mathur, Gaurav Kumar
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Publication number: 20250087251Abstract: Various implementations described herein are directed to a device having a power-gate structure with multiple transistors including a first transistor and a second transistor. The first transistor may be coupled between a first voltage node and a second voltage node, and the second transistor may be coupled between the second voltage node and a third voltage node that is coupled to the second voltage node.Type: ApplicationFiled: September 13, 2023Publication date: March 13, 2025Inventors: Rahul Mathur, Andy Wangkun Chen
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Publication number: 20250078912Abstract: Various implementations described herein are directed to a device having first transistors arranged as cross-coupled inverters coupled between a disconnect node and ground. The device may have second transistors arranged as passgates coupled between the cross-coupled inverters and bitlines. The device may have third transistors coupled between a voltage supply and the disconnect node.Type: ApplicationFiled: August 31, 2023Publication date: March 6, 2025Inventors: Andy Wangkun Chen, Rahul Mathur
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Patent number: 12223010Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.Type: GrantFiled: June 4, 2021Date of Patent: February 11, 2025Assignee: Arm LimitedInventors: Supreet Jeloka, Mudit Bhargava, Saurabh Pijuskumar Sinha, Rahul Mathur
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Patent number: 12087353Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.Type: GrantFiled: August 11, 2022Date of Patent: September 10, 2024Assignee: Arm LimitedInventors: Edward Martin McCombs, Jr., Andrew David Tune, Sean James Salisbury, Rahul Mathur, Hsin-Yu Chen, Phani Raja Bhushan Chalasani
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Publication number: 20240290363Abstract: Various implementations described herein are related to a device with a first clock generator that provides a first pulse signal based on a clock signal, wherein the first clock generator has a first tracking circuit that provides a first reset signal based on the first pulse signal. The device may include a second clock generator that provides a second pulse signal based on the clock signal, wherein the second clock generator has a second tracking circuit that provides a first control signal based on the second pulse signal. Also, the device may include a third clock generator that provides a third pulse signal based on the first reset signal, wherein the third clock generator has a logic circuit that provides a second control signal based on the third pulse signal.Type: ApplicationFiled: February 23, 2023Publication date: August 29, 2024Inventors: Rahul Mathur, Sanjay Mangal, Hemavathi Chaya, Kyung Woo Kim, Pratik Ghanshambhai Satasia, Edward Martin McCombs
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Patent number: 12068025Abstract: Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.Type: GrantFiled: July 1, 2022Date of Patent: August 20, 2024Assignee: Arm LimitedInventors: Rahul Mathur, Edward Martin McCombs, Jr., Hsin-Yu Chen
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Publication number: 20240055047Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Applicant: Arm LimitedInventors: Edward Martin McCombs, JR., Andrew David Tune, Sean James Salisbury, Rahul Mathur, Hsin-Yu Chen, Phani Raja Bhushan Chalasani
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Publication number: 20240038297Abstract: Various implementations described herein are related to a device having bitline drivers coupled to passgates of bitcells via bitlines and buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers. The buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of the selected bitcell to thereby enhance write capability of the selected bitcell.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Rahul Mathur, Mudit Bhargava
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Publication number: 20240036923Abstract: Aspects of the present disclosure relate to an apparatus comprising a plurality of processing elements having a spatial layout, and control circuitry to assign workloads to said plurality of processing elements. The control circuitry is configured to, based on a timing parameter, determine one or more active processing elements to deactivate; determine, based on the spatial layout, one or more inactive processing elements to activate; and deactivate said one or more active processing elements and activate said one or more inactive processing elements.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Rishav ROY, Supreet JELOKA, Shidhartha DAS, Rahul MATHUR
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Publication number: 20240005983Abstract: Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Inventors: Rahul Mathur, Edward Martin McCombs, JR., Hsin-Yu Chen
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Publication number: 20230402092Abstract: Various implementations described herein are directed to a device having memory circuitry with bitlines coupled to an array of bitcells. The device may include precharge circuitry that precharges the bitlines during modes of operation including a standby mode of operation and an active mode of operation. In some instances, the precharge circuitry may include a low power mode of operation that prevents precharge of the bitlines during the standby mode of operation.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Inventors: Rahul Mathur, Hsin-Yu Chen, Phani Raja Bhushan Chalasani, Kyung Woo Kim, Edward Martin McCombs, JR.
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Publication number: 20230354571Abstract: Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried within at least one of the substrate and a dielectric for transmitting electrical signals. The device may be manufactured as a memory device having a memory cell structure with the signal wire buried or partially buried in the substrate.Type: ApplicationFiled: June 23, 2021Publication date: November 2, 2023Inventors: Rahul Mathur, Mudit Bhargava, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Yew Keong Chong
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Patent number: 11682432Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.Type: GrantFiled: June 10, 2021Date of Patent: June 20, 2023Assignee: Arm LimitedInventors: Supreet Jeloka, Saurabh Pijuskumar Sinha, Shidhartha Das, Mudit Bhargava, Rahul Mathur
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Publication number: 20230178538Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Inventors: Rahul Mathur, Xiaoqing Xu, Andy Wangkun Chen, Mudit Bhargava, Brian Tracy Cline, Saurabh Pijuskumar Sinha
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Patent number: 11670363Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.Type: GrantFiled: April 23, 2021Date of Patent: June 6, 2023Assignee: Arm LimitedInventors: Rahul Mathur, Mudit Bhargava, Andy Wangkun Chen
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Patent number: 11569219Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.Type: GrantFiled: October 22, 2020Date of Patent: January 31, 2023Assignee: Arm LimitedInventors: Rahul Mathur, Xiaoqing Xu, Andy Wangkun Chen, Mudit Bhargava, Brian Tracy Cline, Saurabh Pijuskumar Sinha
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Patent number: 11532353Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.Type: GrantFiled: January 29, 2021Date of Patent: December 20, 2022Assignee: Arm LimitedInventors: Mudit Bhargava, Rahul Mathur, Andy Wangkun Chen
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Publication number: 20220391469Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.Type: ApplicationFiled: June 4, 2021Publication date: December 8, 2022Inventors: Supreet Jeloka, Mudit Bhargava, Saurabh Pijuskumar Sinha, Rahul Mathur
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Publication number: 20220343970Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: Rahul Mathur, Mudit Bhargava, Andy Wangkun Chen