Patents by Inventor Rahul Mathur
Rahul Mathur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055047Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Applicant: Arm LimitedInventors: Edward Martin McCombs, JR., Andrew David Tune, Sean James Salisbury, Rahul Mathur, Hsin-Yu Chen, Phani Raja Bhushan Chalasani
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Publication number: 20240036923Abstract: Aspects of the present disclosure relate to an apparatus comprising a plurality of processing elements having a spatial layout, and control circuitry to assign workloads to said plurality of processing elements. The control circuitry is configured to, based on a timing parameter, determine one or more active processing elements to deactivate; determine, based on the spatial layout, one or more inactive processing elements to activate; and deactivate said one or more active processing elements and activate said one or more inactive processing elements.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Rishav ROY, Supreet JELOKA, Shidhartha DAS, Rahul MATHUR
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Publication number: 20240038297Abstract: Various implementations described herein are related to a device having bitline drivers coupled to passgates of bitcells via bitlines and buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers. The buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of the selected bitcell to thereby enhance write capability of the selected bitcell.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Rahul Mathur, Mudit Bhargava
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Publication number: 20240005983Abstract: Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Inventors: Rahul Mathur, Edward Martin McCombs, JR., Hsin-Yu Chen
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Publication number: 20230402092Abstract: Various implementations described herein are directed to a device having memory circuitry with bitlines coupled to an array of bitcells. The device may include precharge circuitry that precharges the bitlines during modes of operation including a standby mode of operation and an active mode of operation. In some instances, the precharge circuitry may include a low power mode of operation that prevents precharge of the bitlines during the standby mode of operation.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Inventors: Rahul Mathur, Hsin-Yu Chen, Phani Raja Bhushan Chalasani, Kyung Woo Kim, Edward Martin McCombs, JR.
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Publication number: 20230354571Abstract: Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried within at least one of the substrate and a dielectric for transmitting electrical signals. The device may be manufactured as a memory device having a memory cell structure with the signal wire buried or partially buried in the substrate.Type: ApplicationFiled: June 23, 2021Publication date: November 2, 2023Inventors: Rahul Mathur, Mudit Bhargava, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Yew Keong Chong
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Patent number: 11682432Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.Type: GrantFiled: June 10, 2021Date of Patent: June 20, 2023Assignee: Arm LimitedInventors: Supreet Jeloka, Saurabh Pijuskumar Sinha, Shidhartha Das, Mudit Bhargava, Rahul Mathur
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Publication number: 20230178538Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Inventors: Rahul Mathur, Xiaoqing Xu, Andy Wangkun Chen, Mudit Bhargava, Brian Tracy Cline, Saurabh Pijuskumar Sinha
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Patent number: 11670363Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.Type: GrantFiled: April 23, 2021Date of Patent: June 6, 2023Assignee: Arm LimitedInventors: Rahul Mathur, Mudit Bhargava, Andy Wangkun Chen
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Patent number: 11569219Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.Type: GrantFiled: October 22, 2020Date of Patent: January 31, 2023Assignee: Arm LimitedInventors: Rahul Mathur, Xiaoqing Xu, Andy Wangkun Chen, Mudit Bhargava, Brian Tracy Cline, Saurabh Pijuskumar Sinha
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Patent number: 11532353Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.Type: GrantFiled: January 29, 2021Date of Patent: December 20, 2022Assignee: Arm LimitedInventors: Mudit Bhargava, Rahul Mathur, Andy Wangkun Chen
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Publication number: 20220391469Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.Type: ApplicationFiled: June 4, 2021Publication date: December 8, 2022Inventors: Supreet Jeloka, Mudit Bhargava, Saurabh Pijuskumar Sinha, Rahul Mathur
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Publication number: 20220343970Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: Rahul Mathur, Mudit Bhargava, Andy Wangkun Chen
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Patent number: 11475944Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.Type: GrantFiled: November 30, 2020Date of Patent: October 18, 2022Assignee: Arm LimitedInventors: Rahul Mathur, Vivek Asthana, Ankur Garcia Goel, Nikhil Kaushik, Rachit Ahuja, Bikas Maiti, Yew Keong Chong
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Patent number: 11468945Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.Type: GrantFiled: October 15, 2020Date of Patent: October 11, 2022Assignee: Arm LimitedInventors: Rahul Mathur, Mudit Bhargava, Joel Thornton Irby, Andy Wangkun Chen
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Publication number: 20220246206Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Inventors: Mudit Bhargava, Rahul Mathur, Andy Wangkun Chen
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Publication number: 20220199125Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.Type: ApplicationFiled: June 10, 2021Publication date: June 23, 2022Inventors: Supreet Jeloka, Saurabh Pijuskumar Sinha, Shidhartha Das, Mudit Bhargava, Rahul Mathur
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Publication number: 20220130816Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.Type: ApplicationFiled: October 22, 2020Publication date: April 28, 2022Inventors: Rahul Mathur, Xiaoqing Xu, Andy Wangkun Chen, Mudit Bhargava, Brian Tracy Cline, Saurabh Pijuskumar Sinha
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Publication number: 20220122655Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.Type: ApplicationFiled: October 15, 2020Publication date: April 21, 2022Applicant: Arm LimitedInventors: Rahul Mathur, Mudit Bhargava, Joel Thornton Irby, Andy Wangkun Chen
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Patent number: 11211111Abstract: A content-addressable memory (CAM) storage element includes bit storage cell bit comparison cells. The bit storage cell is arranged on a first die tier and includes at least one transistor, one or two bit lines, and a storage node. The bit comparison cell is arranged on a second die tier and has a match line, complementary search lines, and at least three transistors. The complementary search lines are decoupled from the bit line(s). A 3D connection couples the storage node to one of the transistors of the second die tier. The CAM cell performs at least one CAM search per clock cycle using at least four transistors per search, including the at least one transistor of the bit storage cell and the at least three transistors of the bit comparison cell, and to output results of the at least one CAM search on the match line.Type: GrantFiled: September 30, 2020Date of Patent: December 28, 2021Assignee: Arm LimitedInventors: Rahul Mathur, Mudit Bhargava, Supreet Jeloka, Andy Wangkun Chen