Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

Abstract: Various implementations described herein refer to an integrated circuit. The integrated circuit may include memory circuitry having multiple bitcell arrays with redundant rows of bitcells. The integrated circuit may include comparator logic disposed outside the memory circuitry to de-assert access to one or more faulty rows of bitcells and to assert access to the redundant rows of bitcells.

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.

Abstract: Various implementations described herein refer to an integrated circuit having dummy wordline driver circuitry coupled to a dummy wordline and dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline. The integrated circuit may include dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry. The dummy wordline tracking circuitry may have one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source.

Abstract: Various implementations described herein refer to an integrated circuit. The integrated circuit may include memory circuitry having multiple bitcell arrays with redundant rows of bitcells. The integrated circuit may include comparator logic disposed outside the memory circuitry to de-assert access to one or more faulty rows of bitcells and to assert access to the redundant rows of bitcells.

Abstract: Various implementations described herein refer to an integrated circuit having dummy wordline driver circuitry coupled to a dummy wordline and dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline. The integrated circuit may include dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry. The dummy wordline tracking circuitry may have one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source.

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.

Abstract: Various implementations described herein are directed to an integrated circuit having level shift circuitry that receives a clock signal in a first voltage domain from a first voltage supply and provides a level shifted clock signal in a second voltage domain based on a second voltage supply that is different than the first voltage supply. The integrated circuit may include clock generator pulse circuitry that receives the clock signal in the first voltage domain from the first voltage supply and receives the level shifted clock signal in the second voltage domain from the level shift circuitry.

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.

Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.