Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

Abstract: A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that includes a drift layer having a first conductivity type, a JFET region that has the first conductivity type in the upper portion of the drift layer, a plurality of well regions having a second conductivity type in an upper portion of the drift layer, each well region forming a respective island within the JFET region when viewed in plan view, and a plurality of source regions having the first conductivity type, where each source region is within a respective one of the well regions. The JFET region comprises a plurality of spaced-apart first JFET sub-regions that each has a first doping concentration and a second JFET sub-region that has a second doping concentration that is lower than the first doping concentration, the second JFET region extending around at least one of the first JFET sub-regions when viewed in plan view.

Abstract: A method of forming a semiconductor device includes forming mesa stripe structure on a semiconductor substrate, the mesa stripe structure including a plurality of alternating trenches and mesa stripes, forming a dielectric spacer on the mesa stripe structure, and forming an etch mask on a portion of the mesa stripe structure. The etch mask covers at least a portion of a first mesa stripe of the plurality of mesa stripes. The dielectric spacer is etched to expose surfaces of the mesa stripes other than the portion of the first mesa stripe that is covered by the etch mask. The etch mask is removed, and a metal layer is formed on the mesa stripe structure. The metal layer forms metal contacts to the exposed surfaces of the mesa stripes. Related semiconductor devices are also disclosed.

Abstract: Provided is a method for determination of a location of a short circuit fault in a generator arrangement, wherein the generator arrangement includes an electrical machine and at least one channel, wherein the or each channel includes a breaker, a converter unit and a set of stator windings of the electrical machine connected to the converter unit via the breaker, wherein upon an occurrence of a short circuit in a channel, the connection between the set of stator windings and the converter unit is interrupted by opening the breaker, wherein depending on at least one measured signal of a measurand, wherein the measured signal is measured by at least one sensor of the electric machine and wherein the measurand describes a torque ripple of the electrical machine, either the electrical machine or the converter unit of the channel is determined as location of the short circuit fault.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A semiconductor device includes a substrate and an epitaxial structure on the substrate. The epitaxial structure includes a drift region and a mesa stripe on the drift region. The mesa stripe includes a channel region on the drift region, a source region on the channel region, and sidewall gate regions on opposite sides of the channel region. The channel region and the source region have a first conductivity type and the sidewall gate regions have a second conductivity type opposite the first conductivity type. The drift region includes a central pillar having the first conductivity type and outer pillars on opposite sides of the central pillar. The outer pillars have the first conductivity type, and the outer pillars and the central pillar form a superjunction structure in the drift region. Related methods are also disclosed.

Abstract: A method of forming a semiconductor device includes providing a first layer including silicon carbide having a first conductivity type, and forming a plurality of doped regions having a second conductivity type in the silicon carbide layer. A second layer including nickel is provided on the first layer and contacts the plurality of doped regions and the first layer. The first layer and the second layer are annealed at a first anneal temperature to form a layer of nickel silicide on the first layer. The first layer and the layer of nickel silicide are annealed at a second anneal temperature that is greater than first anneal temperature to cause the layer of nickel silicide to form ohmic junctions to the plurality of doped regions and to form a Schottky barrier junction to the first layer.

Abstract: A shrinkage detection device for a polymer injection molding apparatus detects a shrinkage experienced by an injection molded element for assessing a quality of the molded element. Shrinkage, along with temperature and pressure of the melt within the mold during cooling, indicates a sufficiency of the resulting molded element for intended purposes. Sufficiency includes parameters such as flexibility, shear strength and longevity, and is accurately performed can replace conventional sample testing of molded articles that are expensive and time consuming.

Abstract: Macroencapsulation devices and related methods of manufacture are described where bonded membranes of a device may be mounted to an associated frame in an arrangement to provide stress relief between the frame and a seal perimeter of the bonded membranes. The seal perimeter may be arranged radially inward from an outer perimeter of the membranes such that when the membranes are mounted to a corresponding perimeter frame, the seal perimeter is spaced radially inwards from the frame with a unbonded portion of the one or more membranes disposed between the frame and seal perimeter.

Abstract: A Schottky diode according to some embodiments includes a silicon carbide drift layer having a first conductivity type, and a junction shielding region in the drift layer. The junction shielding region has a second conductivity type opposite the first conductivity type. The Schottky diode further includes an anode contact on the silicon carbide drift layer. The anode contact includes a refractory metal nitride, and forms a Schottky junction with the drift layer and an ohmic contact to the junction shielding region.

Abstract: A semiconductor device includes a semiconductor layer having a first area and an edge termination area outside the first area. The semiconductor layer has a first conductivity type, an active area in the first area, a test area in the first area adjacent the active area, a first anode contact on the semiconductor layer in the active area, a second anode contact on the semiconductor layer in the test area, and a cathode contact in electrical contact with the semiconductor layer. A related method of testing surge current capability of a semiconductor device includes applying a forward current that is smaller than a maximum forward current of the semiconductor device to a test active area that is within an area inside a main edge termination area of the semiconductor device, and detecting a failure of the semiconductor device in response to the forward current.

Abstract: A semiconductor device includes a semiconductor layer including an active area, a first implanted region within the active area at a surface of the semiconductor layer, and an integrated test area in the semiconductor layer. The integrated test area includes a second implanted region in the semiconductor layer.

Abstract: Systems and methods are provided for a reaction barrier between an electrode active material and a current collector. An electrode may comprise an active material, a metal foil, and a polymer. The polymer (such as polyamide-imide (PAI)) may be configured to provide a carbonized barrier between the active material and the metal foil after pyrolysis.

Abstract: A method for detecting an electrical fault in the stator of an electric machine is provided, wherein the stator includes multiple groups of windings, wherein the windings of each group are assigned to a respective phase of the electric machine, including the steps of: determining a respective current firstly between a subgroup of one of the groups of windings and a distinct further subgroup of the same group of windings and/or secondly between a subgroup of one of the groups of windings and a neutral point, and/or thirdly between a neutral point and either a further neutral point or to a common neutral point connected to at least the neutral point and the further neutral point, evaluating a fault condition, wherein the fulfilment of the fault condition depends on the respective determined current, and outputting a fault signal to personal and/or a device when the fault condition is fulfilled.

Abstract: Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

Abstract: A method of forming a semiconductor device comprises forming a first mask that includes a longitudinally-extending first opening that has a first width on a semiconductor layer structure. A spacer is formed on sidewalls of the first mask that are exposed by the first opening to form a second mask, where the first and second masks comprise a mask structure that has a longitudinally-extending second opening that has a second width that is smaller than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure underneath the third opening.

Abstract: A shrinkage detection device for a polymer injection molding apparatus detects a shrinkage experienced by an injection molded element for assessing a quality of the molded element. Shrinkage, along with temperature and pressure of the melt within the mold during cooling, indicates a sufficiency of the resulting molded element for intended purposes. Sufficiency includes parameters such as flexibility, shear strength and longevity, and is accurately performed can replace conventional sample testing of molded articles that are expensive and time consuming.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to manage video conferencing call data. An example apparatus comprises interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to access input data associated with a first video conferencing device, the first video conferencing device communicatively coupled to a second video conferencing device via a network, generate a representation of the input data when a performance metric corresponding to the network satisfies a threshold value, and transmit the representation to the second video conferencing device via the network.

Abstract: A method of forming a semiconductor device includes etching a semiconductor layer to form a plurality of mesa stripes in the semiconductor layer. The plurality of mesa stripes extend in a first direction and include mesa sidewalls that extend in the first direction and mesa surfaces at opposite ends of the mesa stripes. An additional mesa region is formed at an end of at least one of the mesa stripes. The additional mesa region is electrically insulated from the at least one of the mesa stripes. A semiconductor device structure includes a plurality of mesa stripes that extend in a first direction and include mesa sidewalls that extend in the first direction and mesa end surfaces at opposite ends of the mesa stripes. An additional mesa region that is electrically insulated from the at least one of the mesa stripes is at an end of at least one of the mesa stripes.