Patents by Inventor Rahul R

Rahul R has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11756954
    Abstract: A silicon carbide MOSFET device includes a gate pad area, a main MOSFET area and a secondary MOSFET area. A main source contact is electrically coupled to the source region of each of the main MOSFETs, and a separate secondary source contact is electrically coupled to the source region of each of the secondary MOSFETs. A gate contact electrically connects to each of the insulated gate members of the main and secondary MOSFETs. An asymmetric gate clamping circuit is coupled between the secondary source contact and the gate contact. In a first mode of operation of the MOSFET device the main source contact is electrically coupled with the secondary source contact to activate the gate clamping circuit. When activated, the circuit clamping a gate-to-source voltage to a first clamp voltage in an on-state of the MOSFET device, and to a second clamp voltage in an off-state of the MOSFET device.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: September 12, 2023
    Assignee: SEMIQ INCORPORATED
    Inventors: Rahul R. Potera, Carl A. Witt
  • Patent number: 11749758
    Abstract: A Junction Barrier Schottky (JBS) diode includes an N-type epitaxial layer disposed on SiC substrate, P+ wavy regions are disposed in the epitaxial layer adjoining a top planar surface, each of which is separated from an adjacent one of the wavy regions by a Schottky barrier contact region. P+ island regions are disposed in the Schottky barrier contact regions. A top metal layer is disposed along the top planar surface in direct contact with the Schottky barrier contact regions, the P+ wavy regions, and the P+ island regions, the top metal layer comprising the anode of the JBS diode. A bottom metal layer is disposed beneath the SiC substrate. The bottom metal layer comprises the cathode of the JBS diode.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 5, 2023
    Assignee: SEMIQ INCORPORATED
    Inventors: Rahul R. Potera, Carl A. Witt
  • Patent number: 11741030
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 11728440
    Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 15, 2023
    Assignee: SEMIQ INCORPORATED
    Inventors: James A. Cooper, Rahul R. Potera
  • Patent number: 11681381
    Abstract: An active stylus includes an elongate housing having a tip end and a secondary end, opposite the tip end. An inductive charging coil is mounted within the elongate housing, between the tip end and the secondary end. A magnet configured to magnetically hold the inductive charging coil in a charging position and orientation relative to an inductive charger is moveably mounted within the elongate housing between the tip end and the inductive charging coil.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: June 20, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rahul R. Marwah, Bradley Edgar Clements, Brady James Toothaker
  • Patent number: 11631762
    Abstract: A silicon carbide planar MOSFET includes a junction field-effect transistor (JFET) region that extends up to a top planar surface of the substrate. The JFET region includes a central area, which comprises a portion of the drift region that extends vertically to the top planar surface. First and second sidewall areas are disposed on opposite sides of the central area. The central area has a first lateral width and a first doping concentration. The first and second sidewall areas extend vertically to the top planar surface, with each having a second lateral width. The first and second sidewall areas each have a second doping concentration that is greater than the first doping concentration such that, at a zero bias condition, first and second depletion regions respectively extend only within the first and second sidewall areas of the JFET region.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: April 18, 2023
    Assignee: SEMIQ INCORPORATED
    Inventor: Rahul R. Potera
  • Patent number: 11631841
    Abstract: Methods of preparing an electrode material can include providing silicon particles, forming a mixture comprising the silicon particles dispersed in a solvent, and forming a suspension by adding metal alkoxide or metal aryloxide to the mixture. The methods can also include evaporating the solvent in the suspension to form metal alkoxide or metal aryloxide coated silicon particles. The methods can further include heating the coated silicon particles to form metal oxide coated silicon particles.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 18, 2023
    Assignee: Enevate Corporation
    Inventors: Liwen Ji, Rahul R. Kamath, Ian Russell Browne, Benjamin Yong Park
  • Patent number: 11631773
    Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: April 18, 2023
    Assignee: SEMIQ INCORPORATED
    Inventors: James A. Cooper, Rahul R. Potera
  • Publication number: 20230082780
    Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Inventors: Chenmin SUN, Yipeng WANG, Rahul R. SHAH, Ren WANG, Sameh GOBRIEL, Hongjun NI, Mrittika GANGULI, Edwin VERPLANKE
  • Patent number: 11605806
    Abstract: Methods of forming a composite material film can include providing a layer comprising a carbon precursor and silicon particles on a sacrificial substrate. The methods can also include pyrolysing the carbon precursor to convert the precursor into one or more types of carbon phases to form the composite material film, whereby the sacrificial substrate has a char yield of about 10% or less.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 14, 2023
    Assignee: ENEVATE CORPORATION
    Inventors: Ian Russell Browne, Rahul R. Kamath, Monika Chhorng, Benjamin Yong Park
  • Patent number: 11605713
    Abstract: A silicon carbide MOSFET includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second channel regions of the respective first and second well regions laterally separate the first and second source regions from a JFET region by a channel length. The first and second channel regions extend up to the top surface. The first and second channel regions are each arranged in a wave-shaped pattern at the top surface of the substrate. The wave-shaped pattern extends in first and second lateral directions. In an on-state, current flows laterally from the first and second source regions to the JFET region, and then in a vertical direction down through an extended drain region to the drain region.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: March 14, 2023
    Assignee: SEMIQ INCORPORATED
    Inventors: Rahul R. Potera, Vipindas Pala, Tony Witt
  • Patent number: 11548991
    Abstract: Methods of forming a composite material film can include providing a mixture comprising a precursor and silane-treated silicon particles. The methods can also include pyrolysing the mixture to convert the precursor into one or more carbon phases to form the composite material film with the silicon particles distributed throughout the composite material film.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: January 10, 2023
    Assignee: Enevate Corporation
    Inventors: Ian Russell Browne, Liwen Ji, Rahul R. Kamath, Monika Chhorng
  • Patent number: 11517146
    Abstract: A cooking assistance appliance can include a body, at least one camera, at least one sensor, and an imaging device for capturing an image of a cooking appliance. The cooking appliance can provide for monitoring use of the cooking appliance, as well as assisting the user in operating the cooking appliance. Additionally, the cooking assistance appliance can be integrated into a hood or a microwave oven and vent combination above a stovetop.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: December 6, 2022
    Assignee: Whirlpool Corporation
    Inventors: Collin A. Stipe, Cristiano Vito Pastore, Christopher D. Cullen, Andrea Gallivanoni, Gregory Bauman, Aaron Edward Showers, Rahul S. Dudhe, Natalie Hillmann, Tushar Ashok Kalbande, Ajit Janardan Manohar, Rahul R. Pandey, Neomar Giacomini, Kevin Chase, Josh Abdoo, Larissa Ducci De Araujo, Sugosh Venkataraman, Andrea Ferrise
  • Publication number: 20220357397
    Abstract: A method for detecting an electrical fault in the stator of an electric machine is provided, wherein the stator includes multiple groups of windings, wherein the windings of each group are assigned to a respective phase of the electric machine, including the steps of: determining a respective current firstly between a subgroup of one of the groups of windings and a distinct further subgroup of the same group of windings and/or secondly between a subgroup of one of the groups of windings and a neutral point, and/or thirdly between a neutral point and either a further neutral point or to a common neutral point connected to at least the neutral point and the further neutral point, evaluating a fault condition, wherein the fulfilment of the fault condition depends on the respective determined current, and outputting a fault signal to personal and/or a device when the fault condition is fulfilled.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 10, 2022
    Inventors: Ravindra Bhide, Nuno Miguel Amaral Freire, Rahul R Pillai, Ireneusz Grzegorz Szczesny
  • Publication number: 20220340672
    Abstract: The present disclosure is directed to a method of treating or preventing diabetes, prediabetes, and/or glucose intolerance using TNF Receptor Superfamily Member 25 (TNFRSF25) agonistic antibody or antigen binding fragment thereof. The disclosure is also directed to methods for increasing graft survival and for treating or preventing graft-versus-host disease (GVHD) using TNFRSF25 agonistic antibody.
    Type: Application
    Filed: September 28, 2020
    Publication date: October 27, 2022
    Inventors: Matthew M. SEAVEY, Jeff T. HUTCHINS, Rahul R. JASUJA, A.M. James SHAPIRO, Braulio A. MARFIL-GARZA
  • Publication number: 20220336444
    Abstract: A silicon carbide MOSFET device includes a gate pad area, a main MOSFET area and a secondary MOSFET area. A main source contact is electrically coupled to the source region of each of the main MOSFETs, and a separate secondary source contact is electrically coupled to the source region of each of the secondary MOSFETs. A gate contact electrically connects to each of the insulated gate members of the main and secondary MOSFETs. An asymmetric gate clamping circuit is coupled between the secondary source contact and the gate contact. In a first mode of operation of the MOSFET device the main source contact is electrically coupled with the secondary source contact to activate the gate clamping circuit. When activated, the circuit clamping a gate-to-source voltage to a first clamp voltage in an on-state of the MOSFET device, and to a second clamp voltage in an off-state of the MOSFET device.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Rahul R. Potera, Carl A. Witt
  • Publication number: 20220326789
    Abstract: An active stylus includes an elongate housing having a tip end and a secondary end, opposite the tip end. An inductive charging coil is mounted within the elongate housing, between the tip end and the secondary end. A magnet configured to magnetically hold the inductive charging coil in a charging position and orientation relative to an inductive charger is moveably mounted within the elongate housing between the tip end and the inductive charging coil.
    Type: Application
    Filed: April 9, 2021
    Publication date: October 13, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Rahul R. MARWAH, Bradley Edgar CLEMENTS, Brady James TOOTHAKER
  • Patent number: 11469333
    Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 11, 2022
    Assignee: SEMIQ INCORPORATED
    Inventors: James A. Cooper, Rahul R. Potera
  • Publication number: 20220298252
    Abstract: The present disclosure is directed to a method of treating cancer using a TNFRSF25 agonistic antibody or antigen binding fragment thereof and their combinations with additional therapies such as cancer vaccines and/or checkpoint inhibitors.
    Type: Application
    Filed: August 27, 2020
    Publication date: September 22, 2022
    Inventors: Matthew M. SEAVEY, Jeff T. HUTCHINS, Rahul R. JASUJA
  • Publication number: 20220288716
    Abstract: A flexible conductive gun tube has a plurality of articulated segments connected in series for conducting welding current from a torch handle to a diffuser. Each of the articulated segments has an outer housing having a radially inwardly projecting rim at a first end, and an internal annular groove proximate a second end. A first attachment member includes a ball portion and a first attachment projection that extends away from ball portion and is attached to a first adjacent segment of the gun tube. A second attachment member includes a socket and a second attachment projection that extends axially from the socket past the internal annular groove. The second attachment projection is attached to a second adjacent segment of the gun tube. A retaining ring is located within the internal annular groove, and a biasing member is located axially between the retaining ring and the socket.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Inventor: Rahul R. Bhakta