Patents by Inventor Rahul R. Shah
Rahul R. Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10599602Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: GrantFiled: June 20, 2019Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Publication number: 20190391939Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.Type: ApplicationFiled: February 25, 2019Publication date: December 26, 2019Applicant: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Publication number: 20190310959Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: ApplicationFiled: June 20, 2019Publication date: October 10, 2019Applicant: INTEL CORPORATIONInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10372657Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The low pin count PIPE interface is configured to transfer register commands between the PHY and MAC blocks over the small set of wires in a time-multiplexed manner to support read and write access of the PHY and MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture when operating in a PIPE mode and a serialization and deserialization (SERDES) architecture when operating in a SERDES mode.Type: GrantFiled: December 26, 2016Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10324882Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.Type: GrantFiled: December 29, 2016Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: William R. Halleck, Rahul R. Shah, Venkatraman Iyer
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Patent number: 10248591Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: GrantFiled: December 28, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Patent number: 10152446Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.Type: GrantFiled: October 1, 2016Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Venkatraman Iyer, Mahesh Wagh, William R. Halleck, Rahul R. Shah
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Publication number: 20180191523Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Rahul R. Shah, William R. Halleck, Fulvio Spagna, Venkatraman Iyer
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Publication number: 20180181525Abstract: Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch coupled to the output of the receiver. The PHY includes a clocking multiplexer that includes a first clock input coupled to a recovered clock of the PHY and a second clock input coupled to a p-clock of the MAC; and a clock output configured to output one of the recovered clock or the p-clock based on a selection input value. The PHY includes a bypass multiplexer that includes a first data input coupled to an output of a drift buffer and a second data input coupled to the bypass branch; and a data output configured to output one of the output of the drift buffer or data from the bypass branch based on the section input value of the clocking multiplexer.Type: ApplicationFiled: December 26, 2016Publication date: June 28, 2018Inventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Publication number: 20180095923Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.Type: ApplicationFiled: October 1, 2016Publication date: April 5, 2018Applicant: Intel CorporationInventors: Venkatraman Iyer, Mahesh Wagh, William R. Halleck, Rahul R. Shah
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Patent number: 9779053Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.Type: GrantFiled: December 23, 2014Date of Patent: October 3, 2017Assignee: Intel CorporationInventors: Debendra Das Sharma, Daniel S. Froelich, Venkatraman Iyer, Michelle C. Jen, Rahul R. Shah, Eric M. Lee
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Publication number: 20170109315Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Applicant: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Publication number: 20170109300Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.Type: ApplicationFiled: December 29, 2016Publication date: April 20, 2017Applicant: Intel CorporationInventors: William R. Halleck, Rahul R. Shah, Venkatraman Iyer
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Patent number: 9626321Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.Type: GrantFiled: October 22, 2013Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Patent number: 9422371Abstract: A method for immobilizing an amino-containing material to a substrate is described. The method involves providing a tethering compound with two reactive groups: a substrate reactive group and a fluoroalkoxycarbonyl group. The method further involves preparing a substrate-attached tethering group by reacting the substrate reactive group of the tethering compound with a complementary functional group on the surface of a substrate. The substrate-attached tethering group has a fluoroalkoxycarbonyl group that can be reacted with an amino-containing material to form an immobilization group that connects the amino-containing material to the substrate.Type: GrantFiled: November 3, 2014Date of Patent: August 23, 2016Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Karl E. Benson, Charles M. Leir, George G. I. Moore, Rahul R. Shah
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Publication number: 20160179710Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Applicant: Intel CorporationInventors: Debendra Das Sharma, Daniel S. Froelich, Venkatraman Iyer, Michelle C. Jen, Rahul R. Shah, Eric M. Lee
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Publication number: 20150057438Abstract: A method for immobilizing an amino-containing material to a substrate is described. The method involves providing a tethering compound with two reactive groups: a substrate reactive group and a fluoroalkoxycarbonyl group. The method further involves preparing a substrate-attached tethering group by reacting the substrate reactive group of the tethering compound with a complementary functional group on the surface of a substrate. The substrate-attached tethering group has a fluoroalkoxycarbonyl group that can be reacted with an amino-containing material to form an immobilization group that connects the amino-containing material to the substrate.Type: ApplicationFiled: November 3, 2014Publication date: February 26, 2015Inventors: Karl E. Benson, Charles M. Leir, George G.I. Moore, Rahul R. Shah
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Patent number: 8906703Abstract: A method for immobilizing an amino-containing material to a substrate is described. The method involves providing a tethering compound with two reactive groups: a substrate reactive group and a fluoroalkoxycarbonyl group. The method further involves preparing a substrate-attached tethering group by reacting the substrate reactive group of the tethering compound with a complementary functional group on the surface of a substrate. The substrate-attached tethering group has a fluoroalkoxycarbonyl group that can be reacted with an amino-containing material to form an immobilization group that connects the amino-containing material to the substrate.Type: GrantFiled: September 17, 2007Date of Patent: December 9, 2014Assignee: 3M Innovative Properties CompanyInventors: Karl E. Benson, Charles M. Leir, George G. I. Moore, Rahul R. Shah
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Patent number: 8542046Abstract: Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.Type: GrantFiled: May 4, 2011Date of Patent: September 24, 2013Assignee: Intel CorporationInventors: Eduard Roytman, Jian Xu, Rahul R. Shah, Kambiz R. Munshi, Ronald L. Bedard, Mahalingam Nagarajan
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Patent number: 8357540Abstract: Amino-containing materials can be attached to polymeric materials having a pendant amine capture group that includes a fluoroalkoxycarbonyl group. An amino-containing material can react with the pendant amine capture group by a nucleophilic substitution reaction. The product of the reaction is an alcohol and a pendant group that contains a carbonylimino group. The reaction results in the connection of the amino-containing material to the polymeric material. The polymeric materials are often disposed on a surface of a substrate and the connection of the amino-containing material to the polymeric material results in the immobilization of the amino-containing material on the substrate.Type: GrantFiled: September 17, 2007Date of Patent: January 22, 2013Assignee: 3M Innovative Properties CompanyInventors: George G. I. Moore, Charles M. Leir, Rahul R. Shah