Abstract: According to an embodiment, a method for forming an electronic circuit is provided including forming a netlist of an electronic circuit having a multiplicity of flip-flops, selecting groups of flip-flops from the multiplicity of flip-flops, providing, for each selected group of flip-flops, an error detection circuit for the flip-flops of the group and forming the electronic circuit based on the netlist to include the provided error detection circuits.

Abstract: An oscillator arrangement having an oscillator configured to generate an oscillation signal having two half-cycles, an input configured to receive a synchronization signal including synchronization triggers, a synchronizer configured to reject a synchronization trigger received during a first part of a half-cycle and to synchronize the oscillator to a synchronization trigger received during a second part of the half-cycle, and a controller configured to prolong the second part of the half-cycle in response to receiving a synchronization trigger during the first part of the half-cycle.

Abstract: A communication device having a radio receiver configured to receive a radio signal, a sampling circuit configured to sample the radio signal to generate a sequence of digital sampling values of the radio signal, a correlator configured to correlate the sequence of digital sampling values with each of a plurality of sequences of reference signal values, wherein each sequence of reference signal values corresponds a respective radio communication technology of a plurality of radio communication technologies, a controller configured to select a radio communication technology of the plurality of radio communication technologies based on the results of the correlation, and a data recovery circuit configured to demodulate and decode the radio signal according to the selected radio communication technology.

Abstract: A communication device includes a receiver configured to receive a signal, a sampler configured to sample the signal for each digital value of the predefined sequence of digital values in the signal, a memory configured to store a table giving, for each of a plurality of combinations of one or more preceding first digital values and a following second digital value, a threshold for a signal level to detect the second digital value, an initializer configured to, for a combination in a subset of the plurality of combinations, initialize the table based on a sample of the signal for the second value, and for a combination outside of the subset, select a combination from the subset and initialize the table based on a sample of the signal for the second value of the selected combination.

Abstract: A communication device includes a receiver configured to receive a signal, a sampler configured to sample the signal for each digital value of the predefined sequence of digital values in the signal, a memory configured to store a table giving, for each of a plurality of combinations of one or more preceding first digital values and a following second digital value, a threshold for a signal level to detect the second digital value, an initializer configured to, for a combination in a subset of the plurality of combinations, initialize the table based on a sample of the signal for the second value, and for a combination outside of the subset, select a combination from the subset and initialize the table based on a sample of the signal for the second value of the selected combination.

Abstract: According to an embodiment, a method for forming an electronic circuit is provided including forming a netlist of an electronic circuit having a multiplicity of flip-flops, selecting groups of flip-flops from the multiplicity of flip-flops, providing, for each selected group of flip-flops, an error detection circuit for the flip-flops of the group and forming the electronic circuit based on the netlist to include the provided error detection circuits.

Abstract: A communication device includes a sampler configured to sample an input signal, wherein the sampler is configured to generate a sampled value for each sampling time of a sequence of sampling times, a sequence value generator configured to generate an output value for each sampling time of the sequence of sampling times based on the sampled values, wherein the sequence value generator is configured to set the output value for a sampling time based on the sampled value for the sampling time and based on a limitation of the difference between the output value for the sampling time and the output value for the preceding sampling time in the sequence of sampling times, and an edge detector configured to detect an edge in the input signal based on the output values.

Abstract: An oscillator arrangement having an oscillator configured to generate an oscillation signal having two half-cycles, an input configured to receive a synchronization signal including synchronization triggers, a synchronizer configured to reject a synchronization trigger received during a first part of a half-cycle and to synchronize the oscillator to a synchronization trigger received during a second part of the half-cycle, and a controller configured to prolong the second part of the half-cycle in response to receiving a synchronization trigger during the first part of the half-cycle.

Abstract: According to one embodiment, an arrangement for checking the entropy of a random number sequence is described including a random source configured to provide a random input sequence, a post-processing circuit configured to receive the random input sequence and to generate a random number sequence from the random input sequence by performing a post-processing and a decimation of the random input sequence, an inverse post-processing circuit configured to receive the random number sequence from the post-processing circuit and to generate a processed random number sequence by a processing of the random number sequence that is inverse to the post-processing performed by the post-processing circuit, and an entropy checker configured to check the entropy of the random number sequence based on the processed random number sequence.

Abstract: A communication device includes a sampler configured to sample an input signal, wherein the sampler is configured to generate a sampled value for each sampling time of a sequence of sampling times, a sequence value generator configured to generate an output value for each sampling time of the sequence of sampling times based on the sampled values, wherein the sequence value generator is configured to set the output value for a sampling time based on the sampled value for the sampling time and based on a limitation of the difference between the output value for the sampling time and the output value for the preceding sampling time in the sequence of sampling times, and an edge detector configured to detect an edge in the input signal based on the output values.

Abstract: According to one embodiment, a random number generator is provided including an oscillator arrangement including a first oscillator and a second oscillator. The oscillator arrangement is configured such that a predetermined output state of the second oscillator triggers a transition of the first oscillator from a first oscillation speed to a second oscillation speed and a predetermined output state of the first oscillator triggers a transition of the first oscillator from the second oscillation speed to the first oscillation speed. The random number generator may further include a counter circuit configured to count the number of clock cycles of at least one of the first oscillator or the second oscillator between two transitions of the first oscillator from the first oscillation speed to the second oscillation speed and an output circuit configured to output a random number based on the counted number of clock cycles.

Abstract: According to one embodiment, a random number generator is provided including an oscillator arrangement including a first oscillator and a second oscillator. The oscillator arrangement is configured such that a predetermined output state of the second oscillator triggers a transition of the first oscillator from a first oscillation speed to a second oscillation speed and a predetermined output state of the first oscillator triggers a transition of the first oscillator from the second oscillation speed to the first oscillation speed. The random number generator may further include a counter circuit configured to count the number of clock cycles of at least one of the first oscillator or the second oscillator between two transitions of the first oscillator from the first oscillation speed to the second oscillation speed and an output circuit configured to output a random number based on the counted number of clock cycles.

Abstract: According to one embodiment, an arrangement for checking the entropy of a random number sequence is described including a random source configured to provide a random input sequence, a post-processing circuit configured to receive the random input sequence and to generate a random number sequence from the random input sequence by performing a post-processing and a decimation of the random input sequence, an inverse post-processing circuit configured to receive the random number sequence from the post-processing circuit and to generate a processed random number sequence by a processing of the random number sequence that is inverse to the post-processing performed by the post-processing circuit, and an entropy checker configured to check the entropy of the random number sequence based on the processed random number sequence.

Abstract: A transponder circuit for receiving and processing an ASK signal having modulated communication information is provided. The transponder circuit includes a data receiver configured to receive the ASK signal. A reference clock extractor coupled to the data receiver is configured to extract a reference clock signal from the ASK signal. An amplitude determination unit is coupled to the data receiver and the reference clock extractor, and is configured to determine at least one amplitude value of the received ASK signal in at least one clock cycle of the extracted reference clock signal based on the extracted reference block. A processing unit, which is coupled to the amplitude determination unit, processes the amplitude value such that the communication information is retrieved.

Abstract: An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

Abstract: A transponder power supply for providing a supply current based on an antenna input signal. The transponder power supply comprises an emergency circuit comprising a charging circuit, an emergency capacitor, and an output stage. The charging circuit is configured to charge the emergency capacitor based on the antenna input signal to a maximum voltage which is higher than a voltage of the antenna input signal. The output stage is configured to provide a contribution to the supply current using a charge of the emergency capacitor.

Abstract: An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

Abstract: A voltage regulation and modulation circuit of a contactless device, including an adjustable impedance circuit configured to maintain an amplitude of an input voltage to be less than an amplitude of a reference voltage; a current buffer circuit coupled between the adjustable impedance circuit and a load, and configured to buffer a supply current, which is output from the adjustable impedance circuit, to the load; and a parallel regulator coupled to an output of the current buffer circuit, and configured to maintain a constant supply voltage at the load.

Abstract: A method for generating a signal is provided, the method including: providing a first signal having a first signal frequency; providing a second signal having a second signal frequency or a third signal frequency, wherein the second signal frequency is higher than the third signal frequency; switching the second signal having the second signal frequency to the third signal frequency based on a predefined first signal event of the first signal; and returning the second signal having the third signal frequency to the second signal frequency in response to a predefined second signal event.

Abstract: A method for generating a signal is provided, the method including: providing a first signal having a first signal frequency; providing a second signal having a second signal frequency or a third signal frequency, wherein the second signal frequency is higher than the third signal frequency; switching the second signal having the second signal frequency to the third signal frequency based on a predefined first signal event of the first signal; and returning the second signal having the third signal frequency to the second signal frequency in response to a predefined second signal event.