Abstract: An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

Abstract: A transponder power supply for providing a supply current based on an antenna input signal. The transponder power supply comprises an emergency circuit comprising a charging circuit, an emergency capacitor, and an output stage. The charging circuit is configured to charge the emergency capacitor based on the antenna input signal to a maximum voltage which is higher than a voltage of the antenna input signal. The output stage is configured to provide a contribution to the supply current using a charge of the emergency capacitor.

Abstract: A transponder power supply for providing a supply current based on an antenna input signal. The transponder power supply comprises an emergency circuit comprising a charging circuit, an emergency capacitor, and an output stage. The charging circuit is configured to charge the emergency capacitor based on the antenna input signal to a maximum voltage which is higher than a voltage of the antenna input signal. The output stage is configured to provide a contribution to the supply current using a charge of the emergency capacitor.

Abstract: A transponder circuit for receiving and processing an ASK signal having modulated communication information is provided. The transponder circuit includes a data receiver configured to receive the ASK signal. A reference clock extractor coupled to the data receiver is configured to extract a reference clock signal from the ASK signal. An amplitude determination unit is coupled to the data receiver and the reference clock extractor, and is configured to determine at least one amplitude value of the received ASK signal in at least one clock cycle of the extracted reference clock signal based on the extracted reference block. A processing unit, which is coupled to the amplitude determination unit, processes the amplitude value such that the communication information is retrieved.

Abstract: An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

Abstract: A test circuit provided to monitor a bandgap circuit that outputs a bandgap reference voltage The test circuit includes a reference voltage test module to output a first pass signal when an operating voltage of the bandgap circuit is greater than a first threshold voltage; an output test module to output a second pass signal when an output voltage of the bandgap circuit is greater than a second threshold voltage; and an overdrive test module to output a third pass signal when a minimum operating voltage of the test circuit is detected. Furthermore, a logic circuit is provided and coupled to outputs of each of the test modules. The logic circuit is further configured to output an operating signal, which indicates that the bandgap reference voltage is stable, after receiving the first, second, and third pass signals.

Abstract: A transponder power supply for providing a supply current based on an antenna input signal. The transponder power supply comprises an emergency circuit comprising a charging circuit, an emergency capacitor, and an output stage. The charging circuit is configured to charge the emergency capacitor based on the antenna input signal to a maximum voltage which is higher than a voltage of the antenna input signal. The output stage is configured to provide a contribution to the supply current using a charge of the emergency capacitor.

Abstract: A regulation circuit comprises an error detector, an integrator, and a voltage regulator. The error detector comprises an input for an input voltage, a further input for a reference voltage and an output for an error signal, wherein the error signal depends on the input voltage and the reference voltage. The integrator comprises an input for the error signal and an output for an integrated error signal. The voltage regulator comprises an input for the input voltage and a terminal for the integrated error signal, wherein the voltage regulator is configured to adjust a shunt current responsive to the integrated error signal such that the input voltage is adjusted towards the target voltage.

Abstract: Apparatus for distributing valid random elements, including at least a first module and a second module. The first module is connected to a provider of valid random elements and to the second module. The first module includes a controller that passes valid random elements from the first module to the second module.

Abstract: A voltage regulation and modulation circuit of a contactless device, including an adjustable impedance circuit configured to maintain an amplitude of an input voltage to be less than an amplitude of a reference voltage; a current buffer circuit coupled between the adjustable impedance circuit and a load, and configured to buffer a supply current, which is output from the adjustable impedance circuit, to the load; and a parallel regulator coupled to an output of the current buffer circuit, and configured to maintain a constant supply voltage at the load.

Abstract: A test circuit provided to monitor a bandgap circuit that outputs a bandgap reference voltage The test circuit includes a reference voltage test module to output a first pass signal when an operating voltage of the bandgap circuit is greater than a first threshold voltage; an output test module to output a second pass signal when an output voltage of the bandgap circuit is greater than a second threshold voltage; and an overdrive test module to output a third pass signal when a minimum operating voltage of the test circuit is detected. Furthermore, a logic circuit is provided and coupled to outputs of each of the test modules. The logic circuit is further configured to output an operating signal, which indicates that the bandgap reference voltage is stable, after receiving the first, second, and third pass signals.

Abstract: An integrated circuit including a digital key provider comprising an output and an enable-input, wherein the digital key provider is configured to provide the digital key at the output only when an enable-signal is provided to the enable-input; and a fuse unit comprising a first fuse and a second fuse, wherein the fuse unit is configured to provide the enable-signal to the enable-input when the first fuse is broken while the second fuse is intact.

Abstract: An apparatus for post processing a raw bit sequence generated by a noise source, comprises a derivation unit for deriving a random word from each bit sequence input into the derivation unit and a skip unit for skipping skip sequences of consecutive bits of the raw bit sequence and inputting intervening sub-sequences of bits of the raw bit sequence between the skip sequences into the derivation unit.

Abstract: Random number generator including a first signal source outputting a first signal having a first frequency, a second signal source outputting a second signal having a second frequency which is lower than the first frequency, and time delay elements, wherein the output signals are delayed by a time interval with respect to the input signal. The output of one time delay element is connected in series to the input of another time delay element. The input of the first time delay element is connected to the output of the first signal source. The output of the first signal source and the output of each of the time delay elements are connected to the data input of a corresponding sample and hold element. Clock signal inputs of the sample and hold elements are each connected to the output of the second signal source. Outputs of the sample and hold elements provide random values.

Abstract: An integrated circuit including a digital key provider comprising an output and an enable-input, wherein the digital key provider is configured to provide the digital key at the output only when an enable-signal is provided to the enable-input; and a fuse unit comprising a first fuse and a second fuse, wherein the fuse unit is configured to provide the enable-signal to the enable-input when the first fuse is broken while the second fuse is intact.

Abstract: A regulation circuit comprises an error detector, an integrator, and a voltage regulator. The error detector comprises an input for an input voltage, a further input for a reference voltage and an output for an error signal, wherein the error signal depends on the input voltage and the reference voltage. The integrator comprises an input for the error signal and an output for an integrated error signal. The voltage regulator comprises an input for the input voltage and a terminal for the integrated error signal, wherein the voltage regulator is configured to adjust a shunt current responsive to the integrated error signal such that the input voltage is adjusted towards the target voltage.

Abstract: An apparatus for providing a random bit stream includings a first provider for providing a clock signal, a second provider for providing a sample signal, an activator for activating the first and second providers such that a sampling edge of the sample signal is aligned to an edge of the clock signal. The apparatus further includes a sampler for sampling the clock signal responsive to the sampling edge of the sample signal and for generating a random bit dependent on the sampled state of the clock signal. Further, the apparatus includes a deactivator for deactivating the first and second providers. Successive random bits form a random bit stream.

Abstract: An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and second inverters is connected to the second input of the first inverter; and a third inverter connected between the output of the first and second inverters and the first input of the second inverter.

Abstract: An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and second inverters is connected to the second input of the first inverter; and a third inverter connected between the output of the first and second inverters and the first input of the second inverter.

Abstract: A self-biased cascode current mirror circuit, including a first transistor having a first current electrode, a control electrode, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the first current electrode of the first transistor, and a second current electrode coupled to a terminal; a third transistor having a first current electrode configured to provide an output current, a control electrode coupled to the control electrode of the first transistor and the first current electrode of the third transistor, and a second current electrode; and a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to the terminal.