Patents by Inventor Rainer Steiner

Rainer Steiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9658296
    Abstract: A current sensor device includes a casing having a cavity and a conductor fixedly mounted to the casing. A semiconductor chip configured to sense a magnetic field is arranged in the cavity. An electrically insulating medium is configured to at least partially fill the cavity of the casing.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies AG
    Inventors: Udo Ausserlechner, Volker Strutz, Jochen Dangelmaier, Rainer Steiner
  • Patent number: 9041226
    Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Rainer Steiner, Edward Fuergut, Khalil Hosseini, Georg Meyer-Berg, Joachim Mahler
  • Publication number: 20150015249
    Abstract: A current sensor device includes a casing having a cavity and a conductor fixedly mounted to the casing. A semiconductor chip configured to sense a magnetic field is arranged in the cavity. An electrically insulating medium is configured to at least partially fill the cavity of the casing.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventors: Udo AUSSERLECHNER, Volker STRUTZ, Jochen DANGELMAIER, Rainer STEINER
  • Publication number: 20140264950
    Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Rainer Steiner, Edward Fuergut, Khalil Hosseini, Georg Meyer-Berg, Joachim Mahler
  • Patent number: 8786085
    Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Mathias Vaupel, Rainer Steiner, Werner Robl, Jens Pohl, Joern Plagmann, Gottfried Beer
  • Patent number: 8759207
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Mathias Vaupel, Rainer Steiner, Werner Robl, Jens Pohl, Joem Plagmann, Gottfried Beer
  • Patent number: 8659135
    Abstract: A semiconductor stack and a semiconductor base device with a wiring substrate and an intermediate wiring board for a semiconductor device stack is disclosed. In one embodiment, a semiconductor chip is arranged between the intermediate wiring board and the wiring substrate, which is electrically connected by way of the wiring substrate on the one hand to external contacts on the underside of the wiring substrate and on the other hand to contact terminal areas in the edge regions of the wiring substrate. The intermediate wiring board has angled-away external flat conductors, which are electrically connected in the contact terminal areas of the wiring board. Furthermore, on the upper side of the intermediate wiring board, arranged on the free ends of the internal flat conductors are external contact terminal areas, which correspond in size and arrangement to external contacts of a semiconductor device to be stacked.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: February 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Michael Bauer, Ulrich Bachmaier, Robert-Christian Hagen, Jens Pohl, Rainer Steiner, Hermann Vllsmeler, Holger Woerner, Bernhard Zuhr
  • Publication number: 20130309864
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Application
    Filed: November 8, 2012
    Publication date: November 21, 2013
    Inventors: Hans-Joachim BARTH, Mathias VAUPEL, Rainer STEINER, Werner ROBL, Jens POHL, Joern PLAGMANN, Gottfried BEER
  • Patent number: 8334202
    Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies AG
    Inventors: Jens Pohl, Hans-Joachim Barth, Gottfried Beer, Rainer Steiner, Werner Robl, Mathias Vaupel
  • Patent number: 8330273
    Abstract: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Jens Pohl, Rainer Steiner
  • Patent number: 8330274
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • Publication number: 20120080791
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Patent number: 8148257
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • Publication number: 20120074574
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Patent number: 8072071
    Abstract: A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: December 6, 2011
    Assignee: Infineon Technologies AG
    Inventors: Rainer Steiner, Jens Pohl, Werner Robl, Markus Brunnbauer, Gottfried Beer
  • Publication number: 20110291274
    Abstract: A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips.
    Type: Application
    Filed: August 8, 2011
    Publication date: December 1, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thorsten Meyer, Gerald Ofner, Rainer Steiner
  • Publication number: 20110291256
    Abstract: A semiconductor chip includes a contact pad on a main surface of the chip. An electrically conductive layer is applied onto the contact pad. The main surface of the semiconductor chip is covered with an insulating layer. An electrically conductive contact area is formed within the insulating layer such that the contact area and the insulating layer include coplanar exposed surfaces and the contact area is electrically connected with the electrically conductive layer and includes an extension which is greater than the extension of the electrically conductive layer along a direction parallel to the main surface of the semiconductor chip.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Inventors: Rainer Steiner, Jens Pohl, Werner Robl, Gottfried Beer
  • Publication number: 20110101532
    Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 5, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Jens Pohl, Hans-Joachim Barth, Gottfried Beer, Rainer Steiner, Werner Robl, Mathias Vaupel
  • Publication number: 20110024915
    Abstract: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.
    Type: Application
    Filed: October 14, 2010
    Publication date: February 3, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Markus Brunnbauer, Jens Pohl, Rainer Steiner
  • Patent number: 7863088
    Abstract: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: January 4, 2011
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Jens Pohl, Rainer Steiner