Patents by Inventor Raj K. Bansal

Raj K. Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266630
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: January 5, 2024
    Date of Patent: April 1, 2025
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20250069952
    Abstract: Systems and methods for mitigating crack meandering, are disclosed herein. In some embodiments, the method includes forming a metallic layer over planned scribe regions of an upper surface of a wafer, then selectively patterning and/or etching the metallic layer to form a plurality of isolated lines over the planned scribe regions. The method can then include depositing a passivation material over the plurality of isolated lines. Adjacent isolated lines can be separated from each other by a small enough distance to disrupt the deposition process, thereby creating a gap in the passivation material between each of the adjacent isolated lines. The gaps and/or trenches formed in the top surface of the wafer by etching the passivation material through the gaps can help attract cracks during a stealth dicing process, thereby reducing the amount the cracks meander away from the planned scribe regions.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 27, 2025
    Inventors: Vibhav Gupta, Wei Chang Mendoza Wong, Xinyun Chen, Raj K. Bansal, Teng Leong Tan
  • Patent number: 12230608
    Abstract: A semiconductor device has first and second dies forming a die stack. Molding material encapsulates the die stack and forms an upper molded surface of the die stack. First conductive traces are coupled to the first die and extend from between the first and second die to corresponding first via locations in the molding material beyond a first side edge of the die stack. Second conductive traces coupled to an active surface of the second die opposite the first die extend to corresponding second via locations. Each first via location is vertically aligned with one of the second via locations. Through mold vias extend through the molding material between vertically aligned via locations to contact with corresponding conductive traces of the first and second dies, while the molding material that extends between the first conductive traces and the upper molded surface is free from any TMV.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: February 18, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Travis M. Jensen, Raj K. Bansal
  • Publication number: 20250029957
    Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.
    Type: Application
    Filed: October 3, 2024
    Publication date: January 23, 2025
    Inventors: Koichi Kawai, Raj K. Bansal, Takehiro Hasegawa, Chang H. Siau
  • Publication number: 20240371824
    Abstract: A semiconductor device including a semiconductor die and an encapsulant material disposed at the edges of the semiconductor die and among the plurality of fin shape structures. The semiconductor die further includes a substrate, a functional die region disposed in a center of the semiconductor die, the functional die region having a stack layer structure within which a plurality of dielectric layers and a plurality of electrically conductive layers alternatively stacked, and a die edge region disposed at edges of the semiconductor die, the die edge region including a plurality of fin shape structures protruding along a horizontal direction to a sidewall of the semiconductor device.
    Type: Application
    Filed: March 14, 2024
    Publication date: November 7, 2024
    Inventors: Yichen Wang, Tsung Che Tsai, Vibhav Gupta, Wei Chang Wong, Raj K. Bansal
  • Patent number: 12136607
    Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: November 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Koichi Kawai, Raj K. Bansal, Takehiro Hasegawa, Chang H. Siau
  • Patent number: 12125789
    Abstract: According to one or more embodiments, a method of manufacturing a semiconductor device including a plurality of main circuit regions arranged in a matrix and a scribe region provided between the main circuit regions is provided. The method includes: forming a first insulating film; forming a low-k film; forming a plurality of penetrating portions penetrating through the low-k film; and forming a second insulating film under low-coverage film-forming conditions to form cavities in the plurality of through-holes.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: October 22, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita, Raj K. Bansal
  • Publication number: 20240145425
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20240088100
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 14, 2024
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Publication number: 20240072002
    Abstract: A semiconductor device assembly can include an assembly substrate having a top surface with a die stack thereat. The die stack can include a first and a second die, and each dies can include a die substrate with a top and a bottom surface. The top surface can include a first region a first distance from the bottom surface, and a second region a second distance, greater than the first distance, from the bottom surface and with a bond pad thereat. The bottom surface of the first die can bond with the top surface of the assembly substrate, and the bottom surface of the second die can bond with the first region of the first die top surface. In some embodiments, the assembly can further include additional die stacks and/or additional dies within one or more die stacks.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventor: Raj K. Bansal
  • Patent number: 11876068
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: January 16, 2024
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20240014083
    Abstract: A method of making a semiconductor device assembly is provided. The method comprises attaching a first semiconductor device to an upper surface of a substrate and disposing a stencil over the upper surface of the substrate. The stencil includes (i) an opening and (ii) a cavity in which the first semiconductor device is disposed. The method further comprises screen-printing an epoxy material into the opening and onto the upper surface of the substrate, removing the stencil, and planarizing an upper surface of the epoxy material to form an epoxy spacer.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 11, 2024
    Inventors: Hem P. Takiar, Raj K. Bansal, Jian Wei Lim, Li Wang, Jungbae Lee
  • Patent number: 11810822
    Abstract: Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Keizo Kawakita, Raj K. Bansal, Tsung Che Tsai
  • Publication number: 20230326867
    Abstract: Methods, systems, and devices for techniques for forming a device with scribe asymmetry are described. Circuits (e.g., arrays of memory cells) may be printed on a wafer and separated by scribes of various widths to increase an array efficiency of a fabrication process. For example, a scribe that extends in a first direction may have a width in a second direction. A first subset of scribes may have a first width, where one or more structures may be placed in the first subset of scribes to facilitate die testing and integration. A second subset of scribes may have a second width. In some examples, the structures may not be placed in the second subset of scribes and, accordingly, the second width may be less than the first width.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Inventors: Anna Maria Conti, Raj K. Bansal
  • Patent number: 11769756
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: September 26, 2023
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Publication number: 20230290684
    Abstract: Structures and methods for separating semiconductor wafers into individual dies are disclosed. A semiconductor wafer or panel can include a crack assist structure in a scribe junction. The crack assist structure can include a plurality of vertical walls extending at least partially through a thickness of the wafer. In some embodiments, the plurality of vertical walls can be coupled to a weak interface. The weak interface can guide cracks that form during the dicing process in a direction along the walls, away from active circuitry. After dicing, the resulting semiconductor devices can include a plurality of vertical walls extending at least partially through a thickness of the semiconductor device. Each of the plurality of vertical walls can include at least a portion extending substantially parallel to a sidewall of the semiconductor device.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Inventors: Wei Chang Wong, Radhakrishna Kotti, Raj K. Bansal, Youngik Kwon, Po Chih Yang, Venkateswarlu Bhavanasi
  • Patent number: 11705432
    Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
  • Publication number: 20230090041
    Abstract: Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Applicant: Micron Technology, Inc.
    Inventors: SHIGERU SUGIOKA, KEIZO KAWAKITA, RAJ K. BANSAL, TSUNG CHE TSAI
  • Publication number: 20230061258
    Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.
    Type: Application
    Filed: April 11, 2022
    Publication date: March 2, 2023
    Inventors: Koichi Kawai, Raj K. Bansal, Takehiro Hasegawa, Chang H. Siau
  • Publication number: 20230055425
    Abstract: A semiconductor device has first and second dies forming a die stack. Molding material encapsulates the die stack and forms an upper molded surface of the die stack. First conductive traces are coupled to the first die and extend from between the first and second die to corresponding first via locations in the molding material beyond a first side edge of the die stack. Second conductive traces coupled to an active surface of the second die opposite the first die extend to corresponding second via locations. Each first via location is vertically aligned with one of the second via locations. Through mold vias extend through the molding material between vertically aligned via locations to contact with corresponding conductive traces of the first and second dies, while the molding material that extends between the first conductive traces and the upper molded surface is free from any TMV.
    Type: Application
    Filed: September 17, 2021
    Publication date: February 23, 2023
    Inventors: Travis M. Jensen, Raj K. Bansal