Patents by Inventor Raj K. Bansal

Raj K. Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10943841
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20210066247
    Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
  • Publication number: 20210020592
    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Patent number: 10847482
    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20200227327
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Patent number: 10651100
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20190355682
    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20190355631
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal