Abstract: Embodiments of an access point for an expanded wireless local area network are described and depicted.

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are associated into groups 10, 11, and tone ordering, gain selection, and/or bit swapping within the processing system are done within the members of a group 10, 11. This idea is applicable both to tone ordering etc., following the training stage, and also to the dynamic configuration changes subsequently, for example, bit swapping. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the memory requirements of the encoder and decoder.

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are associated into groups 10, 11, and tone ordering, gain selection, and/or bit swapping within the processing system are done within the members of a group 10, 11. This idea is applicable both to tone ordering etc., following the training stage, and also to the dynamic configuration changes subsequently, for example, bit swapping. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the memory requirements of the encoder and decoder.

Abstract: An improved ADSL system with improved data rate is disclosed. In one embodiment, the upstream data bit rate is increased by extending the upstream transmission band. In another embodiment, the downstream data is also increased by extending the downstream transmission band.

Abstract: A method of controlling a data flow, a transmitter and a data transmission system are described. For example, in a method of controlling a data flow of a transmitter, first data is received at a first interface. The first data is buffered in a buffer. The first data is output via a second interface. Information is determined regarding an estimated amount of second data comprising payload data output via the first interface until a filling level of the buffer will reach a predetermined threshold. An amount of the payload data output via the first interface is adjusted based on the information. The payload data is then output via the first interface. Similarly, a transmitter includes an interface to output payload data and a control signal, and a buffer to buffer further data received via the interface wherein the control signal controls a flow of said further data.

Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. A bank may be further divided into a plurality of blocks. A cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.

Abstract: A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. A redundancy decoder employs the decoded signal and the first error indication signal (or transformed versions thereof) to perform redundancy decoding.

Abstract: A system for processing a data signal (such as an ADSL or VDSL signal) includes a demodulator, a first decoder unit, such as a convolutional encoder or a QAM decoder, for receiving the output of the demodulator, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. The decoded signal is passed through a de-interleaving unit to form a de-interleaved signal. The first location signal is passed to an identifier unit which receives it, and from it produces a second error indication signal indicative of the errors in the de-interleaved signal. The de-interleaved signal and the second error indication signal are transmitted to a redundancy decoder which employs them to perform redundancy decoding.

Abstract: A memory array comprises memory cells of the dynamic type having a first and a second port. A cache memory is connected to the address and data paths of the first and second ports. A refresh operation is performed through one of said ports. When a refresh operation is performed through said one port, a read operation can be performed through the cache memory in parallel.

Abstract: A discrete multitone (DMT) transceiver communicates with multiple channels generates and receives DMT symbols each having a duration of a timeslot. A transmitter portion of the transceiver includes a symbol processor which generates symbols for multiple channels sequentially, and stores the generated symbols in a buffer until they are transmitted. A receiver portion simultaneously receives symbols on multiple channels and stores the symbols in a buffer, from which the symbols on different channels are read and processed sequentially. To reduce the rate of communication on a given channel, the symbol processors may be idle in respect of some of the timeslots corresponding to that channel. The transceiver may alternatively be an OFDM transceiver.

Abstract: An improved ADSL system with improved data rate is disclosed. In one embodiment, the upstream data bit rate is increased by extending the upstream transmission band. In another embodiment, the downstream data is also increased by extending the downstream transmission band.

Abstract: An IC having an array of memory cells that can be accessed through two different ports is described. Read/write operation is performed through one of the ports. The refresh of the memory cell is performed through the other port. In one embodiment, the other port is only used internally to the memory array.

Abstract: An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.

Abstract: An integrated circuit having a BIST control unit for testing a plurality of memory banks simultaneously is described. The BIST control unit is coupled to a plurality of comparator units. In one embodiment, a comparator unit is coupled to a memory bank to facilitate parallel testing.

Abstract: An integrated circuit (1) includes a processing device (2), a program interface (4, 5) coupled to the processing device (2), a data interface (6, 7) coupled to the processing device. The program interface (4, 5) includes a first address bus (4) and a first data bus (5) and the data interface (6, 7) includes a second address bus (6) and a second data bus (7). The integrated circuit also includes address and data bus switching devices (18) and a control device (16). The address bus switching device (18) is coupled to the first and second address buses (4, 6) and adapted to be coupled to an external address bus (11) and the data bus switching device (18) is adapted to be coupled to an external data bus (12) and is coupled to the first and second data buses (5, 7). The control device (16) is coupled to the processing device (2), the address bus switching device (18) and the data bus switching device (18).

Abstract: The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile memory cell which is modified to permanently retain data by using one refresh port to transmit an active low voltage signal and configuring one terminal of the storage transistor to receive either an active high or low voltage signal.

Abstract: An IC having an array of memory cells that can be accessed through two different ports is described. Read/write operation is performed through one of the ports. The refresh of the memory cell is performed through the other port. In one embodiment, the other port is only used internally to the memory array.

Abstract: An IC with a memory array comprises a redundancy unit. The redundancy unit includes a tag portion, an address portion, and a redundant memory cell portion. A comparator determines whether an address of a read or a write command matches with the address stored in the address portion of the redundancy unit and switches from the normal data path to the memory cell portion of the redundancy unit.

Abstract: A memory array includes sense amplifiers with a portion for amplifying a low level signal and a portion for amplifying a high level signal on bitlines. In an improved method for operating the memory array, the first portion of the sense amplifier is enabled before the second portion of the sense amplifier. The two-step amplification process reduces noise injection and lowers peak current consumption during the sense operation.

Abstract: A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh operation is described. The refresh operation is allocated to the port that is not externally accessed. When accesses through both ports are requested, a wait cycle for one of the access requests is inserted until the refresh is terminated.