Patents by Inventor Raj Kumar Jain

Raj Kumar Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6704232
    Abstract: An integrated memory device comprises a multitude of sense amplifiers which output an amplified data signal on a data line. The data line is forced to a precharge potential when idle. A transistor connects the data line to a precharge potential. The memory device avoids the kickback effect during a data read operation.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: March 9, 2004
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Publication number: 20030212722
    Abstract: A processor for performing fast Fourier-type transform operations is disclosed. At least one multiplier and a plurality of adders are provided to perform butterfly operations comprising three multiply operations and a plurality of add operations. Internal wordlengths are wider than wordlengths of input values to reduce rounding error.
    Type: Application
    Filed: August 2, 2002
    Publication date: November 13, 2003
    Applicant: Infineon Technologies Aktiengesellschaft.
    Inventors: Raj Kumar Jain, Seo How Low
  • Publication number: 20030212721
    Abstract: A processor for performing fast Fourier-type transform operations is described. Butterfly operations are performed on input values a prescribed number of times, a butterfly operation comprising three multiply operations and a plurality of add operations.
    Type: Application
    Filed: May 7, 2002
    Publication date: November 13, 2003
    Applicant: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Publication number: 20030204665
    Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. A bank may be further divided into a plurality of blocks. A cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.
    Type: Application
    Filed: April 26, 2002
    Publication date: October 30, 2003
    Inventors: Raj Kumar Jain, Rudi Frenzel
  • Patent number: 6628551
    Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: September 30, 2003
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Patent number: 6628541
    Abstract: An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: September 30, 2003
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Patent number: 6621752
    Abstract: In an IC having memory cells, a write operation is performed on a word within a particular row of memory cells. The other words within the same row are refreshed during the same cycle. In another embodiment, dual port memory cells are employed to enable a second row of memory cells to be refreshed during the same cycle.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: September 16, 2003
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Patent number: 6621304
    Abstract: A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: September 16, 2003
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Publication number: 20030088744
    Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. Such a mapping causes sequential data bytes to be stored in alternate banks. Each bank may be further divided into a plurality of blocks. By staggering or synchronizing the processors to execute the computer program such that each processor access a different block during the same cycle, the processors can access the memory simultaneously.
    Type: Application
    Filed: April 4, 2002
    Publication date: May 8, 2003
    Applicant: Infineon Technologies Aktiengesellschaft
    Inventors: Raj Kumar Jain, Rudi Frenzel, Markus Terschluse, Christian Horak, Stefan Uhlemann
  • Publication number: 20030088801
    Abstract: An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.
    Type: Application
    Filed: April 2, 2002
    Publication date: May 8, 2003
    Applicant: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Publication number: 20030085742
    Abstract: A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.
    Type: Application
    Filed: April 4, 2002
    Publication date: May 8, 2003
    Applicant: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Patent number: 6549451
    Abstract: A memory cell is provided with a first access transistor coupled to a first terminal of the storage transistor and a second access transistor coupled to a second terminal of the storage transistor is disclosed. The gates of the access transistors are coupled to word lines. In the inactive state, the word lines comprise a negative voltage to reduce leakage current from the memory cell.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: April 15, 2003
    Inventor: Raj Kumar Jain
  • Patent number: 6545905
    Abstract: A memory cell having a plurality of first access transistors are coupled to a first terminal of the storage transistor and a second access transistors coupled to a second terminal of the storage transistor is disclosed. The access transistors serve as access ports for the memory cell.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: April 8, 2003
    Assignee: Infineon Technologies AG
    Inventor: Raj Kumar Jain
  • Publication number: 20030063516
    Abstract: In an IC having memory cells, a write operation is performed on a word within a particular row of memory cells. The other words within the same row are refreshed during the same cycle. In another embodiment, dual port memory cells are employed to enable a second row of memory cells to be refreshed during the same cycle.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 3, 2003
    Inventor: Raj Kumar Jain
  • Publication number: 20030063517
    Abstract: An integrated circuit having a BIST control unit for testing a plurality of memory banks simultaneously is described. The BIST control unit is coupled to a plurality of comparator units. In one embodiment, a comparator unit is coupled to a memory bank to facilitate parallel testing.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 3, 2003
    Inventor: Raj Kumar Jain
  • Publication number: 20030063515
    Abstract: A memory array comprises memory cells of the dynamic type having a first and a second port. A cache memory is connected to the address and data paths of the first and second ports. A refresh operation is performed through one of said ports. When a refresh operation is performed through said one port, a read operation can be performed through the cache memory in parallel.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 3, 2003
    Inventor: Raj Kumar Jain
  • Patent number: 6510075
    Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The storage transistor comprises a gate oxide formed from a material having a high dielectric constant to increase the capacitance.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: January 21, 2003
    Inventor: Raj Kumar Jain
  • Publication number: 20020186580
    Abstract: The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile memory cell which is modified to permanently retain data by using one refresh port to transmit an active low voltage signal and configuring one terminal of the storage transistor to receive either an active high or low voltage signal.
    Type: Application
    Filed: April 4, 2002
    Publication date: December 12, 2002
    Applicant: Infineon Technologies Aktiengesellschaft
    Inventor: Raj Kumar Jain
  • Publication number: 20020176290
    Abstract: An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.
    Type: Application
    Filed: April 24, 2002
    Publication date: November 28, 2002
    Inventor: Raj Kumar Jain
  • Patent number: 6487107
    Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. During a write 0 operation, a degraded logic 0 is written into the memory cell. By storing a degraded logic 0, the leakage current is reduced.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: November 26, 2002
    Assignee: Infineon Technologies AG
    Inventor: Raj Kumar Jain