Patents by Inventor Raj Mehrotra
Raj Mehrotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128316Abstract: A semiconductor device comprising a substrate having a first conductivity type, the substrate having a top surface and a bottom surface, a first buried layer disposed in the substrate at a first depth from the top surface, wherein the first buried layer has a second conductivity type and a first doping concentration, a second buried layer adjacent and surrounding the first buried layer at the first depth, wherein the second buried layer has the second conductivity type and a second doping concentration, wherein the second doping concentration is less than the first doping concentration, and an isolation trench disposed in the substrate and surrounding the second buried layer, wherein the isolation trench extends from the top surface of the substrate to a second depth, the second depth exceeding the first depth.Type: ApplicationFiled: September 25, 2023Publication date: April 18, 2024Inventors: Saumitra Raj Mehrotra, Ronghua Zhu, Todd Roggenbauer
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Patent number: 11961907Abstract: A transistor includes a trench formed in a semiconductor substrate. A conductive spacer is formed in the trench and offset from a first sidewall of the trench. A dielectric material is formed in the trench and surrounds the conductive spacer. A drift region is formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench. A drain region is formed in the drift region adjacent to a second portion of the second sidewall. A first gate region overlaps a portion of the drift region and is formed separate from the conductive spacer.Type: GrantFiled: October 24, 2022Date of Patent: April 16, 2024Assignee: NXP USA, INC.Inventor: Saumitra Raj Mehrotra
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Patent number: 11777002Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.Type: GrantFiled: December 6, 2021Date of Patent: October 3, 2023Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Patent number: 11640997Abstract: A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.Type: GrantFiled: March 4, 2021Date of Patent: May 2, 2023Assignee: NXP B.V.Inventors: Saumitra Raj Mehrotra, Kejun Xia
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Publication number: 20230053824Abstract: A transistor includes a trench formed in a semiconductor substrate. A conductive spacer is formed in the trench and offset from a first sidewall of the trench. A dielectric material is formed in the trench and surrounds the conductive spacer. A drift region is formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench. A drain region is formed in the drift region adjacent to a second portion of the second sidewall. A first gate region overlaps a portion of the drift region and is formed separate from the conductive spacer.Type: ApplicationFiled: October 24, 2022Publication date: February 23, 2023Inventor: Saumitra Raj Mehrotra
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Patent number: 11515416Abstract: A transistor includes a trench formed in a semiconductor substrate. A conductive spacer is formed in the trench and offset from a first sidewall of the trench. A dielectric material is formed in the trench and surrounds the conductive spacer. A drift region is formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench. A drain region is formed in the drift region adjacent to a second portion of the second sidewall. A first gate region overlaps a portion of the drift region and is formed separate from the conductive spacer.Type: GrantFiled: September 23, 2020Date of Patent: November 29, 2022Assignee: NXP USA, INC.Inventor: Saumitra Raj Mehrotra
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Publication number: 20220344506Abstract: A laterally-diffused metal-oxide semiconductor, “LDMOS”, device and a method of making the same. The device includes a gate located on a major surface of a semiconductor die, a source region located in the die on a first side of the gate, a drain drift region located in the die on a second side of the gate opposite the first side, a first spacer located adjacent to a first sidewall of the gate on the first side of the gate, and a second spacer located adjacent to a second sidewall of the gate on the second side of the gate. The second spacer is located between the gate and the drain drift region. The second spacer comprises a proximal spacer portion and a distal spacer portion. The proximal spacer portion is located between the gate and the distal spacer portion. The proximal spacer portion and the distal spacer portion define a recess.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: Saumitra Raj Mehrotra, Kejun Xia
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Publication number: 20220285564Abstract: A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Inventors: Saumitra Raj Mehrotra, Kejun Xia
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Patent number: 11387348Abstract: Disclosed herein is a transistor structure that is formed by forming a sidewall spacer along a first vertical component sidewall of a trench wherein no sidewall spacer is formed along a second vertical component sidewall of the trench. During an etching of a dielectric layer in the trench, the sidewall spacer protects a first portion of the dielectric layer from being etched while a second portion of the dielectric layer along the second sidewall is etched. A portion of a control terminal can be formed in the space where the second portion is removed.Type: GrantFiled: November 22, 2019Date of Patent: July 12, 2022Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
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Patent number: 11329156Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.Type: GrantFiled: December 16, 2019Date of Patent: May 10, 2022Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
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Publication number: 20220093752Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Publication number: 20220093793Abstract: A transistor includes a trench formed in a semiconductor substrate. A conductive spacer is formed in the trench and offset from a first sidewall of the trench. A dielectric material is formed in the trench and surrounds the conductive spacer. A drift region is formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench. A drain region is formed in the drift region adjacent to a second portion of the second sidewall. A first gate region overlaps a portion of the drift region and is formed separate from the conductive spacer.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventor: Saumitra Raj Mehrotra
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Patent number: 11282956Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.Type: GrantFiled: December 16, 2019Date of Patent: March 22, 2022Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
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Patent number: 11227921Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.Type: GrantFiled: November 22, 2019Date of Patent: January 18, 2022Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Patent number: 11217675Abstract: A semiconductor device includes a trench in a semiconductor material having a device section and a termination section. A gate structure is located in the trench. With some embodiments, the transverse cross-sectional width of the termination section is wider than the transverse cross-sectional width of the device section.Type: GrantFiled: March 31, 2020Date of Patent: January 4, 2022Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Publication number: 20210305385Abstract: A semiconductor device includes a trench in a semiconductor material having a device section and a termination section. A gate structure is located in the trench. With some embodiments, the transverse cross-sectional width of the termination section is wider than the transverse cross-sectional width of the device section.Type: ApplicationFiled: March 31, 2020Publication date: September 30, 2021Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Patent number: 11075110Abstract: A method includes forming separate conductive trench structures in a trench and then removing an upper portion of one of the conductive structures where the remaining portion serves as field gate for a transistor. Removing the upper portion includes forming a second trench. The second trench is filled with a gate material that is used as a gate for the transistor. The transistor includes a source region for the transistor on the side of the trench and a drain region for the transistors on the other side of the trench, wherein the drain region includes a portion located at an upper portion of a semiconductor material. The transistor includes a channel region having a portion located along a sidewall of a trench.Type: GrantFiled: March 31, 2020Date of Patent: July 27, 2021Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Publication number: 20210184034Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.Type: ApplicationFiled: December 16, 2019Publication date: June 17, 2021Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
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Publication number: 20210159319Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Publication number: 20210159323Abstract: Disclosed herein is a transistor structure that is formed by forming a sidewall spacer along a first vertical component sidewall of a trench wherein no sidewall spacer is formed along a second vertical component sidewall of the trench. During an etching of a dielectric layer in the trench, the sidewall spacer protects a first portion of the dielectric layer from being etched while a second portion of the dielectric layer along the second sidewall is etched. A portion of a control terminal can be formed in the space where the second portion is removed.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote