Patents by Inventor Raj Mehrotra
Raj Mehrotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210126125Abstract: A transistor device includes a substrate, a first current-carrying region having a first lateral width, and a second current-carrying region. A first trench is formed between the first current-carrying region and the second current-carrying region. The first trench includes a first vertical component sidewall coupled to the first current-carrying region and a second vertical component sidewall coupled to the second current-carrying region. A first termination region includes a first termination portion coupled to the first current-carrying region, a second termination portion coupled to the second current-carrying region, and a first trench termination portion coupled to the first trench. The first trench and the first trench termination portion surround a portion of the first current-carrying region, and the second current-carrying region and the second termination portion surrounds a portion of the first trench and the first trench termination portion.Type: ApplicationFiled: December 31, 2020Publication date: April 29, 2021Inventors: Bernhard Grote, Saumitra Raj Mehrotra, Ljubo Radic
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Patent number: 10833174Abstract: A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.Type: GrantFiled: October 26, 2018Date of Patent: November 10, 2020Assignee: NXP USA, INC.Inventors: Bernhard Grote, Ljubo Radic, Saumitra Raj Mehrotra, Tania Tricia-Marie Thomas, Mark Edward Gibson
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Patent number: 10749028Abstract: Disclosed herein is a conductive structure that serves as both a control terminal and a field plate for a transistor. The transistor includes a channel region including a portion located in a vertical sidewall of semiconductor material that separates an upper level portion and a lower level portion of the semiconductor material. An extended drain region includes a portion located in the lower portion of the semiconductor material. The conductive structure is laterally adjacent to the vertical sidewall and includes a first vertical side and an opposite second vertical side with the first vertical side being closer to the vertical component sidewall. The first side is vertically closer to the lower level portion of the semiconductor material than the second vertical side.Type: GrantFiled: November 30, 2018Date of Patent: August 18, 2020Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Patent number: 10749023Abstract: A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.Type: GrantFiled: October 30, 2018Date of Patent: August 18, 2020Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
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Publication number: 20200176599Abstract: Disclosed herein is a conductive structure that serves as both a control terminal and a field plate for a transistor. The transistor includes a channel region including a portion located in a vertical sidewall of semiconductor material that separates an upper level portion and a lower level portion of the semiconductor material. An extended drain region includes a portion located in the lower portion of the semiconductor material. The conductive structure is laterally adjacent to the vertical sidewall and includes a first vertical side and an opposite second vertical side with the first vertical side being closer to the vertical component sidewall. The first side is vertically closer to the lower level portion of the semiconductor material than the second vertical side.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: SAUMITRA RAJ MEHROTRA, Bernhard Grote, Ljubo Radic
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Patent number: 10672903Abstract: A semiconductor device includes a drain region for a transistor, a drain active area directly below the drain region, a drift area directly below an insolation structure, and an accumulation area directly below a gate structure of the transistor. The semiconductor device includes a first selectively doped implant region of a first concentration of a first conductivity type extending to a first depth. The first selectively doped implant region is located in the drift area, the drain active area, and the accumulation area. The semiconductor device includes a second selectively doped implant region of a second concentration of the first conductivity type and extending to a second depth less than the first depth. The second concentration is less than the first concentration. The second selectively doped implant region is located the drain active area, but not in the accumulation area.Type: GrantFiled: July 25, 2018Date of Patent: June 2, 2020Assignee: NXP USA, INC.Inventors: Xin Lin, Saumitra Raj Mehrotra, Ronghua Zhu
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Publication number: 20200135916Abstract: A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Inventors: Saumitra Raj MEHROTRA, Bernhard GROTE, Ljubo RADIC
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Publication number: 20200135896Abstract: A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Bernhard Grote, Ljubo Radic, Saumitra Raj Mehrotra, Tania Tricia-Marie Thomas, Mark Edward Gibson
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Patent number: 10607880Abstract: A continuous buried doped isolation region in a substrate of a die. The substrate includes an isolation ring structure surrounding a first area of the die. The continuous buried doped isolation region is of a net first conductivity type and is located in the first area. The continuous buried doped isolation region including a first portion having a net first conductivity type dopant concentration of at least a first level located in an interior region of the first area and extending to a sidewall of the isolation ring structure. The first portion does not extend to the sidewall of the isolation ring structure in a location of a corner area of the first area. The corner area is defined by the isolation ring structure. A second portion of the continuous buried doped isolation region in the corner area has a net first conductivity type dopant concentration of a second level that is lower than the first level.Type: GrantFiled: August 30, 2018Date of Patent: March 31, 2020Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Tanuj Saxena, Ljubo Radic, Bernhard Grote
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Publication number: 20200098912Abstract: A transistor device includes a conductive structure located in a trench of semiconductor material. The conductive structure is located closer to a first sidewall of the trench than to a second sidewall of the trench. The conductive structure serves as a control terminal and a field plate for a transistor. At a first location in the trench where the conductive structure functions as a control terminal for a transistor, the conductive structure is located a first lateral distance from the trench sidewall with dielectric located in between. At a second location in the trench where the conductive structure functions as a field plate, the conductive structure is located a second lateral distance from the trench sidewall with dielectric located in between. The second lateral distance is greater than the first lateral distance.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: BERNHARD GROTE, Ljubo Radic, Saumitra Raj Mehrotra, Tania Tricia-Marie Thomas, Mark Edward Gibson
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Patent number: 10600911Abstract: A transistor includes a trench formed in a semiconductor substrate. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to a first sidewall of the trench. A first field plate is formed in the trench with the first field plate located between a second edge of the gate electrode and a second sidewall of the trench. A dielectric material is formed in the trench with the dielectric material having a first thickness between the first sidewall and a first edge of the first field plate, and a second thickness between the second sidewall and a second edge of the first field plate, the second thickness larger than the first thickness.Type: GrantFiled: September 26, 2017Date of Patent: March 24, 2020Assignee: NXP USA, INC.Inventors: Bernhard Grote, Saumitra Raj Mehrotra, Ljubo Radic, Vishnu Khemka, Mark Edward Gibson
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Patent number: 10600879Abstract: A trench structure is located directly laterally between a first well and a first source region for a first transistor and the second well region with a second source for a second transistor. The trench structure includes a first gate structure for the first transistor, a second gate structure for the second transistor, a first conductive field plate structure, and a second conductive field plate structure. The first gate structure, the first field plate structure, the second field plate structure, and the second gate structure are located in the trench structure in a lateral line between the first well region and the second well region. The trench structure includes a dielectric separating the first field plate structure and the second field plate structure from each other in the lateral line. A drain region for the first transistor and the second transistor includes a portion located directly below the trench structure.Type: GrantFiled: March 12, 2018Date of Patent: March 24, 2020Assignee: NXP USA, INC.Inventors: Bernhard Grote, Saumitra Raj Mehrotra, Ljubo Radic, Vishnu Khemka
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Publication number: 20200075393Abstract: A continuous buried doped isolation region in a substrate of a die. The substrate includes an isolation ring structure surrounding a first area of the die. The continuous buried doped isolation region is of a net first conductivity type and is located in the first area. The continuous buried doped isolation region including a first portion having a net first conductivity type dopant concentration of at least a first level located in an interior region of the first area and extending to a sidewall of the isolation ring structure. The first portion does not extend to the sidewall of the isolation ring structure in a location of a corner area of the first area. The corner area is defined by the isolation ring structure. A second portion of the continuous buried doped isolation region in the corner area has a net first conductivity type dopant concentration of a second level that is lower than the first level.Type: ApplicationFiled: August 30, 2018Publication date: March 5, 2020Inventors: Saumitra Raj Mehrotra, Tanuj Saxena, Ljubo Radic, Bernhard Grote
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Publication number: 20200035827Abstract: A semiconductor device includes a drain region for a transistor, a drain active area directly below the drain region, a drift area directly below an insolation structure, and an accumulation area directly below a gate structure of the transistor. The semiconductor device includes a first selectively doped implant region of a first concentration of a first conductivity type extending to a first depth. The first selectively doped implant region is located in the drift area, the drain active area, and the accumulation area. The semiconductor device includes a second selectively doped implant region of a second concentration of the first conductivity type and extending to a second depth less than the first depth. The second concentration is less than the first concentration. The second selectively doped implant region is located the drain active area, but not in the accumulation area.Type: ApplicationFiled: July 25, 2018Publication date: January 30, 2020Inventors: Xin Lin, Saumitra Raj Mehrotra, Ronghua Zhu
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Patent number: 10522677Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench and the vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A first dielectric material is formed in the trench between the first sidewall and the vertical field plate. A second dielectric material is formed in the trench between the vertical field plate and the second sidewall with the second dielectric material having a dielectric constant lower than that of the first dielectric material.Type: GrantFiled: September 26, 2017Date of Patent: December 31, 2019Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
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Patent number: 10424646Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench. The vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A dielectric material is formed in the trench between the first sidewall and the vertical field plate. An air cavity is formed in the trench between the vertical field plate and the second sidewall with the air cavity having a dielectric constant lower than that of the dielectric material.Type: GrantFiled: September 26, 2017Date of Patent: September 24, 2019Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
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Patent number: 10418483Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.Type: GrantFiled: October 30, 2017Date of Patent: September 17, 2019Assignee: NXP B.V.Inventors: Bernhard Grote, Xin Lin, Saumitra Raj Mehrotra, Ljubo Radic, Ronghua Zhu
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Publication number: 20190280094Abstract: A trench structure is located directly laterally between a first well and a first source region for a first transistor and the second well region with a second source for a second transistor. The trench structure includes a first gate structure for the first transistor, a second gate structure for the second transistor, a first conductive field plate structure, and a second conductive field plate structure. The first gate structure, the first field plate structure, the second field plate structure, and the second gate structure are located in the trench structure in a lateral line between the first well region and the second well region. The trench structure includes a dielectric separating the first field plate structure and the second field plate structure from each other in the lateral line. A drain region for the first transistor and the second transistor includes a portion located directly below the trench structure.Type: ApplicationFiled: March 12, 2018Publication date: September 12, 2019Inventors: BERNHARD GROTE, Saumitra Raj Mehrotra, Ljubo Radic, Vishnu Khemka
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Publication number: 20190097045Abstract: A transistor includes a trench formed in a semiconductor substrate. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to a first sidewall of the trench. A first field plate is formed in the trench with the first field plate located between a second edge of the gate electrode and a second sidewall of the trench. A dielectric material is formed in the trench with the dielectric material having a first thickness between the first sidewall and a first edge of the first field plate, and a second thickness between the second sidewall and a second edge of the first field plate, the second thickness larger than the first thickness.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: BERNHARD GROTE, SAUMITRA RAJ MEHROTRA, LJUBO RADIC, VISHNU KHEMKA, MARK EDWARD GIBSON
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Publication number: 20190097046Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench and the vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A first dielectric material is formed in the trench between the first sidewall and the vertical field plate. A second dielectric material is formed in the trench between the vertical field plate and the second sidewall with the second dielectric material having a dielectric constant lower than that of the first dielectric material.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: SAUMITRA RAJ MEHROTRA, Ljubo Radic, Bernhard Grote