Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: A signal processing circuit, which is within a satellite reception assembly, may be operable to analyze actual frequency information corresponding to a plurality of downconverted signals. Each of the downconverted signals may be downconverted using one or more corresponding local oscillators (LOs). Based on the analyzing, one or more of the following may be determined: one or more frequency offsets associated with the one or more corresponding LOs and one or more actual guard bands. The signal processing circuit may generate information on the determined frequency offsets and the determined actual guard bands. The signal processing circuit may perform, based on the generated information, one or both of a band stacking operation and a channel stacking operation so as to prevent channels/bands being stacked on each other or being overlapped. The signal processing circuit may perform, based on the generated information, frequency corrections for channel tuning in a gateway.

Abstract: Systems and methods are provided for dynamically biasing power amplifiers. In particular, dynamic biasing of a power amplifier may be controlled, with the controlling comprising receiving an input signal that is to be amplified; processing the input signal; generating based on said processing of the input signal input signal, a plurality of control signals comprising at least one biasing control signal; and applying the plurality of control signals to one or more control elements that are used in driving and/or control of the power amplifier. The one or more control elements may comprise at least one biasing component that adjusts biasing applied to power amplifier.

Abstract: A monolithic integrated circuit for use in a microwave backhaul system may comprise a plurality of microwave transceivers and outdoor-unit to indoor-unit (ODU/IDU) interface circuitry. The monolithic integrated circuit may be configurable into an all-outdoor configuration in which the ODU/IDU interface circuitry is disabled. The monolithic integrated circuit may be configurable into a split-indoor-and-outdoor configuration in which the ODU/IDU interface circuitry is enabled to communicate signals between an outdoor unit of the microwave backhaul system and an indoor unit of the microwave backhaul system. While the monolithic integrated circuit is configured in the split-indoor-and-outdoor configuration, the ODU/IDU interface circuitry may be configurable to operate in at least a non-stacking mode and a stacking mode.

Abstract: A microwave backhaul system may comprise a monolithic integrated circuit comprising an on-chip transceiver, digital baseband processing circuitry, and auxiliary interface circuitry. The on-chip transceiver may process a microwave signal from an antenna element to generate a first pair of quadrature baseband signals and convey the first pair of phase-quadrature baseband signals to the digital baseband processing circuitry. The auxiliary interface circuitry may receive one or more auxiliary signals from a source that is external to the monolithic integrated circuit and convey the one or more auxiliary signals to the digital baseband processing circuitry. The digital baseband processing circuitry may be operable to process signals to generate one or more second pairs of phase-quadrature digital baseband signals.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: Methods and systems for a configurable low-noise amplifier with programmable band-selection filters may comprise a low-noise amplifier (LNA) with a low pass filter coupled to a first input of the LNA and a high pass filter coupled to a second input of the LNA. The low pass filter and the high pass filter may also be coupled to a signal source input. Signals may be received in a pass band of the high pass filter and a pass band of the low pass filter. Input signals in the pass band of the one filter (but not signals in the pass band of the other filter) may be amplified by coupling the one input of the LNA to ground and coupling the other filter to ground utilizing a shunt resistor. The filters may be configurable and may each comprise at least one inductor and at least one capacitor.

Abstract: Methods and systems are provided for band translation with protection. A signal processing circuitry (chip) may be configured to handle a plurality of signals, comprising at least a first signal corresponding to internal communication within an in-premises network and at least a second signal originating from a source external to the in-premises network; and to process on-chip the plurality of input signals, to generate one or more output signals. In this regard, at least one output signal may comprise components corresponding to the first signal and the second signal; and the processing may be configured to mitigate on-chip, during generating of the one or more outputs, at least one effect of including in the at least one output signal a first component corresponding to one of the first signal and the second signal on a second component corresponding to the other one of the first signal and the second signal.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions.

Abstract: A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations.

Abstract: A system for processing signals may be configured to apply digital conversion to analog signals, and to apply, prior to the analog-to-digital conversion, a gain to at least a portion of the analog signals. The gain may be controlled and/or adjusted based on processing of digital output generated based on the analog-to-digital conversion. The system may comprise a plurality of sampling slices, which may be configured to provide the analog-to-digital conversion in interleaved (e.g., time-interleaved) manner. Each of the sampling slices may comprise a dedicated gain element, for applying gain to signals handled by the corresponding slice. The gain applied by the gain elements of the sampling slices may be controlled, independently, collectively, and/or in based on grouping into subsets. The gain may be controlled based on application of a particular gain control algorithm, which may be selected from a plurality of predefined algorithms.

Abstract: Methods and systems for improved cross polarization rejection and tolerating of coupling between satellite signals may comprise receiving radio frequency (RF) signals on a chip, where the RF signals comprising a desired signal and at least one crosstalk signal. The received RF signals may be down-converted to baseband frequencies, and the down-converted signals are converted to digital signals. Crosstalk may be determined by estimating complex coupling coefficients between the received RF signals utilizing a de-correlation algorithm across a frequency bandwidth comprising the desired and crosstalk signals. The down-converted signals may be low-pass filtered and summed with an output signal from a cancellation filter. The complex coupling coefficients may be determined utilizing the de-correlation algorithm on the summed signals, and may be used to configure the cancellation filter.

Abstract: A signal processing circuit, which is within a satellite reception assembly, may be operable to analyze actual frequency information corresponding to a plurality of downconverted signals. Each of the downconverted signals may be downconverted using one or more corresponding local oscillators (LOs). Based on the analyzing, one or more of the following may be determined: one or more frequency offsets associated with the one or more corresponding LOs and one or more actual guard bands. The signal processing circuit may generate information on the determined frequency offsets and the determined actual guard bands. The signal processing circuit may perform, based on the generated information, one or both of a band stacking operation and a channel stacking operation so as to prevent channels/bands being stacked on each other or being overlapped. The signal processing circuit may perform, based on the generated information, frequency corrections for channel tuning in a gateway.

Abstract: An electronic device may be operable to sample a signal during an analog-to-digital conversion using an analog-to-digital converter in the electronic device, and the signal may comprise a wide bandwidth and a plurality of channels. The electronic device may adaptively change a sample rate of the sampling to move aliasing out of a region of one or more desired channels of the plurality of channels. The electronic device may change the sample rate using a variable oscillator in the electronic device. The change of the sample rate may comprise, for example, increasing or decreasing the sample rate by a particular percentage. In response to the change of the sample rate, the electronic device may perform, using a variable rate interpolator in the electronic device, variable rate interpolation. The variable rate interpolator may comprise, for example, a finite impulse response filter.

Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.

Abstract: Methods and systems for a baseband cross-bar may comprise receiving one or more radio frequency (RF) signals in a wireless communication device via antennas coupled to a plurality of receiver paths in the wireless device. The received RF signals may be converted to baseband frequencies. One or more of the down-converted signals may be coupled to receiver paths utilizing a baseband cross-bar. The baseband cross-bar may comprise a plurality of switches, which may comprise CMOS transistors. In-phase and quadrature signals may be processed in the one or more of the plurality of receiver paths. The one or more RF signals comprise cellular signals and/or global navigation satellite signals. A single-ended received RF signal may be converted to a differential signal in one or more of the plurality of receiver paths. The baseband cross-bar may be controlled utilizing a reduced instruction set computing (RISC) processor.

Abstract: A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions.