Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

Abstract: An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage.

Abstract: An apparatus to monitor and control a switching rate in a switch includes a differentiator circuit including a capacitor and a configurable resistor. The differentiator circuit further includes an input terminal of the capacitors configured to receive a first voltage from a switch and a differentiator node configured to receive a differentiated voltage based on the first voltage. The apparatus includes a peak detector circuit coupled to the differentiator node and configured to detect a peak value of the differentiated voltage. The apparatus further includes a driver circuit coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak value of the differentiated voltage.

Abstract: A resonant line driver for driving capacitive-loads includes a driver series-coupled to an energy transfer inductor L1, driving signal energy at a signal frequency through L1. A switch array is controlled to switch L1 between multiple electrodes according to a switching sequence, each electrode characterized by a load capacitance CL. L1 and CL form a resonator circuit in which signal energy cycles between L1 and CL at the signal frequency. The switch array switches L1 between a current electrode and a next electrode at a zero_crossing when signal energy in the energy transfer inductor is at a maximum and signal energy in the load capacitance of the current electrode is at a minimum. An amplitude control loop controls signal energy delivered to the L1CL resonator circuit, and a frequency control loop controls signal frequency/phase. In an example application, the resonant driver provides line drive for a mutual capacitance touch screen.

Abstract: Modulating a gate drive current supplied to an output drive switch coupled to an electric motor by performing at least the following: obtain a gate drive current modulation profile, supply, based on the gate drive current modulation profile, a first gate drive current level as the gate drive current when the output drive switch is operating within a first region, drop the first gate drive current level to a second gate drive current level when the output drive switch transitions from the first region to operating within a Miller region, increase the second gate drive current level to a third gate drive current level within the Miller region, and set the gate drive current to a fourth gate drive current level when the output drive switch transitions from the Miller region to operating within a third region.

Abstract: Modulating a gate drive current supplied to an output drive switch coupled to an electric motor by performing at least the following: obtain a gate drive current modulation profile, supply, based on the gate drive current modulation profile, a first gate drive current level as the gate drive current when the output drive switch is operating within a first region, drop the first gate drive current level to a second gate drive current level when the output drive switch transitions from the first region to operating within a Miller region, increase the second gate drive current level to a third gate drive current level within the Miller region, and set the gate drive current to a fourth gate drive current level when the output drive switch transitions from the Miller region to operating within a third region.

Abstract: Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle.

Abstract: An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.

Abstract: An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage.

Abstract: Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle.

Abstract: In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.

Abstract: A high bandwidth Hall sensor includes a high bandwidth path and a low bandwidth path. The relatively high offset (from sensor offset) of the high bandwidth path is estimated using a relatively low offset generated by the low bandwidth path. The relatively high offset of the high bandwidth path is substantially reduced by combining the output of the high bandwidth path with the output of the low bandwidth path to generate a high bandwidth, low offset output. The offset can be further reduced by including transimpedance amplifiers in the high bandwidth sensors to optimize the frequency response of high bandwidth Hall sensor.

Abstract: An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.

Abstract: An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage.

Abstract: A first amplifier has an input to receive a Hall-signal output current from a first Hall element and has an output to output feedback current in response to the received Hall-signal output current. The Hall-signal output current is impeded by an impedance of the first Hall element. The feedback current is coupled to counterpoise the Hall-signal output current at the input, and a voltage at the output is an amplified Hall output signal. A second amplifier generates a high-frequency portion output signal in response to a difference between the amplified Hall output signal and a Hall-signal output signal from a second Hall element. A filter reduces high-frequency content of the high-frequency portion output signal and generates an offset correction signal. A third amplifier generates a corrected Hall signal in response to a difference between the amplified Hall output signal and the offset correction signal.

Abstract: Circuitry and methods for sampling a signal are disclosed. An example of the circuitry includes a node for coupling the circuitry to the signal being sampled and a plurality of capacitors, wherein each capacitor is selectively coupled to the node by a switch. An analog-to-digital converter is coupled to the node and is for measuring the voltages of individual ones of the plurality of capacitors and converting the voltages to digital signals. Delay circuitry is coupled to each of the switches, the delay circuitry is for closing one switch at a time for a predetermined period.

Abstract: Modulating a gate drive current supplied to an output drive switch coupled to an electric motor by performing at least the following: obtain a gate drive current modulation profile, supply, based on the gate drive current modulation profile, a first gate drive current level as the gate drive current when the output drive switch is operating within a first region, drop the first gate drive current level to a second gate drive current level when the output drive switch transitions from the first region to operating within a Miller region, increase the second gate drive current level to a third gate drive current level within the Miller region, and set the gate drive current to a fourth gate drive current level when the output drive switch transitions from the Miller region to operating within a third region.

Abstract: A high bandwidth Hall sensor includes, for example, a Hall element for generating a first polarity Hall-signal output current. An amplifier receives, at a first input, the first polarity Hall-signal output current and outputs a feedback current of a second polarity opposite the first polarity in response. The feedback current is coupled to the first input, and the feedback current suppresses an instantaneous voltage generated by the first polarity first Hall element output current at the first input. In an embodiment, the feedback current suppresses the instantaneous voltage generated by first polarity Hall element output current such that the effects of the Hall element source impedance are reduced.

Abstract: An apparatus includes a voltage divider circuit including a plurality of series- connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage.

Abstract: An apparatus to monitor and control a switching rate in a switch includes a differentiator circuit including a capacitor and a configurable resistor. The differentiator circuit further includes an input terminal of the capacitors configured to receive a first voltage from a switch and a differentiator node configured to receive a differentiated voltage based on the first voltage. The apparatus includes a peak detector circuit coupled to the differentiator node and configured to detect a peak value of the differentiated voltage. The apparatus further includes a driver circuit coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak value of the differentiated voltage.