Patents by Inventor Rajasekhar Reddy Allu

Rajasekhar Reddy Allu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11537299
    Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 27, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Mihir Narendra Mody, Niraj Nandan, Rajasekhar Reddy Allu
  • Publication number: 20220294960
    Abstract: Disclosed examples include integrated circuits, merge circuits and methods of processing multiple-exposure image data, in which a single pre-processing circuit is used for pre-processing first input exposure data associated with a first exposure of the image, and then for pre-processing second input exposure data associated with a second exposure of the image, and the first and second pre-processed exposure data are merged to generate merged image data for tone mapping and other post-processing. An example merge circuit includes a configurable gain circuit to apply a gain to the first and/or second exposure data, as well as a configurable weighting circuit with a weight calculation circuit and a motion adaptive filter circuit to compute a first and second weight values for merging the pre-processed first and second exposure data.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 15, 2022
    Inventors: Shashank Dabral, Rajasekhar Reddy Allu
  • Publication number: 20220263979
    Abstract: In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: Gang HUA, Mihir Narendra MODY, Rajasekhar Reddy ALLU, Niraj NANDAN, Shashank DABRAL
  • Patent number: 11375131
    Abstract: Disclosed examples include integrated circuits, merge circuits and methods of processing multiple-exposure image data, in which a single pre-processing circuit is used for pre-processing first input exposure data associated with a first exposure of the image, and then for pre-processing second input exposure data associated with a second exposure of the image, and the first and second pre-processed exposure data are merged to generate merged image data for tone mapping and other post-processing. An example merge circuit includes a configurable gain circuit to apply a gain to the first and/or second exposure data, as well as a configurable weighting circuit with a weight calculation circuit and a motion adaptive filter circuit to compute a first and second weight values for merging the pre-processed first and second exposure data.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 28, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shashank Dabral, Rajasekhar Reddy Allu
  • Publication number: 20220174249
    Abstract: A method for local automatic white balance (AWB) of wide dynamic range (WDR) images is provided that includes collecting statistics for local AWB by an image signal processor (ISP) from a first WDR image generated by the ISP, receiving, by the ISP, a plurality of local gain lookup tables (LUTs), one for each color channel, wherein the plurality of local gain LUTs is generated using the statistics, and applying, by the ISP, a gain value to each pixel in a second WDR image generated by the ISP, wherein the gain value for the pixel is determined by the ISP using the local gain LUT for the color channel of the pixel.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 2, 2022
    Inventors: Gang Hua, Shashank Dabral, Mihir Narendra Mody, Rajasekhar Reddy Allu, Niraj Nandan
  • Patent number: 11330153
    Abstract: In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 10, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Gang Hua, Mihir Narendra Mody, Rajasekhar Reddy Allu, Niraj Nandan, Shashank Dabral
  • Publication number: 20220114120
    Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Inventors: Mihir MODY, Niraj NANDAN, Hetul SANGHVI, Brian CHAE, Rajasekhar Reddy ALLU, Jason A.T. JONES, Anthony LELL, Anish REGHUNATH
  • Publication number: 20220058768
    Abstract: A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Inventors: Niraj NANDAN, Rajasekhar Reddy ALLU, Mihir Narendra MODY
  • Patent number: 11237991
    Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mihir Mody, Niraj Nandan, Hetul Sanghvi, Brian Chae, Rajasekhar Reddy Allu, Jason A. T. Jones, Anthony Lell, Anish Reghunath
  • Publication number: 20210407120
    Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventors: Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody, Gang Hua, Brian Okchon Chae, Shashank Dabral, Hetul Sanghvi, Vikram VijayanBabu Appia, Sujith Shivalingappa
  • Patent number: 11170464
    Abstract: A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: November 9, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Niraj Nandan, Rajasekhar Reddy Allu, Mihir Narendra Mody
  • Publication number: 20210326050
    Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 21, 2021
    Inventors: Mihir Narendra MODY, Niraj NANDAN, Rajasekhar Reddy ALLU
  • Patent number: 11145079
    Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: October 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody, Gang Hua, Brian Okchon Chae, Shashank Dabral, Hetul Sanghvi, Vikram VijayanBabu Appia, Sujith Shivalingappa
  • Publication number: 20210209737
    Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.
    Type: Application
    Filed: December 11, 2020
    Publication date: July 8, 2021
    Inventors: Gang Hua, Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody
  • Publication number: 20210209041
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
    Type: Application
    Filed: December 31, 2020
    Publication date: July 8, 2021
    Inventors: Niraj Nandan, Rajasekhar Reddy Allu, Brian Chae, Mihir Mody
  • Publication number: 20210209722
    Abstract: A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.
    Type: Application
    Filed: June 23, 2020
    Publication date: July 8, 2021
    Inventors: Niraj NANDAN, Rajasekhar Reddy ALLU, Mihir Narendra MODY
  • Publication number: 20210136358
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Niraj Nandan, Brian Chae, Mihir Mody, Rajasekhar Reddy Allu
  • Publication number: 20210042891
    Abstract: A method for geometrically correcting a distorted input frame and generating an undistorted output frame includes capturing and storing an input frame in an external memory, allocating an output frame with an output frame size and dividing the output frame into output blocks, computing a size of the input blocks in the input image corresponding to each output blocks, checking if the size of the input blocks is less than the size of the internal memory and if not dividing until the required input block size of divided sub blocks is less than the size of the internal memory, programming an apparatus with input parameters, fetching the input blocks into an internal memory, processing each of the divided sub blocks sequentially and processing the next output block in step until all the output blocks are processed; and composing the output frame for each of the blocks in the output frame.
    Type: Application
    Filed: October 27, 2020
    Publication date: February 11, 2021
    Inventors: Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody, Gang Hua, Brian Okchon Chae, Shashank Dabral, Hetul Sanghvi, Vikram VijayanBabu Appia, Sujith Shivalingappa
  • Publication number: 20200396356
    Abstract: In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Gang HUA, Mihir Narendra MODY, Rajasekhar Reddy ALLU, Niraj NANDAN, Shashank DABRAL
  • Publication number: 20200389581
    Abstract: Disclosed examples include integrated circuits, merge circuits and methods of processing multiple-exposure image data, in which a single pre-processing circuit is used for pre-processing first input exposure data associated with a first exposure of the image, and then for pre-processing second input exposure data associated with a second exposure of the image, and the first and second pre-processed exposure data are merged to generate merged image data for tone mapping and other post-processing. An example merge circuit includes a configurable gain circuit to apply a gain to the first and/or second exposure data, as well as a configurable weighting circuit with a weight calculation circuit and a motion adaptive filter circuit to compute a first and second weight values for merging the pre-processed first and second exposure data.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Shashank Dabral, Rajasekhar Reddy Allu